95 lines
2.7 KiB
ArmAsm
95 lines
2.7 KiB
ArmAsm
# @(#)99 1.9 src/bos/kernel/ml/POWER/wipl.s, sysml, bos411, 9432B411a 8/10/94 10:43:03
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#*****************************************************************************
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#
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# COMPONENT_NAME: (SYSML) Kernel Assembler Code
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#
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# FUNCTIONS: wipl
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#
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# ORIGINS: 27
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#
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# IBM CONFIDENTIAL -- (IBM Confidential Restricted when
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# combined with the aggregated modules for this product)
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# SOURCE MATERIALS
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# (C) COPYRIGHT International Business Machines Corp. 1989, 1994
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# All Rights Reserved
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#
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# US Government Users Restricted Rights - Use, duplication or
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# disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
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#
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#****************************************************************************
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.file "wipl.s"
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.machine "com"
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#
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# common include files
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#
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##print(off);
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include(iplcb.m4)
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##print(on);
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# absolute low storage addressability
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.using low, 0
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##page;
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#**********************************************************************
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#
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# NAME: warm ipl
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#
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# FUNCTION: Setup for and call ROS warm ipl code.
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#
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#
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# INPUT STATE:
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# Called from reboot() and sr_slih() with translation enabled
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# R3 contains ROS Warm IPL Entry Address
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# R4 contains value to put into SR15
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#
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# OUTPUT STATE:
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# Translation disabled, interrupt prefix enabled
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# Upon exit to ROS warm ipl, R3 will contain
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# the address of the iplcb.
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#
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# EXECUTION ENVIRONMENT:
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# Supervisor state : Yes
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#
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#**********************************************************************
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#*************************************************************************
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# Turn translation off and interrupt prefix on. Get the pointer to
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# ipl control block info section.
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#*************************************************************************
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S_PROLOG(wipl)
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cal r8,(MSR_ME + MSR_IP)(0) # set ME + IP flag
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mtmsr r8 # set it in the msr
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mtsr 15,r4 # load sr15 with seg reg value
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isync # make sure DR and SR are noticed
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# NOTE: we have to do the above 'mtsr' to ZERO SR15 prior to the load from
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# ROS address space. This is due to the fact that on POWER boxes, the
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# T bit is still interpreted even in real mode....with the ROS addresses
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# having a 0xF in the high nibble, it tries to use SR15, which usually
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# has the T bit set due to previous I/O
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l r8,0(r3) # load ros entry point
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cau r8,r8,0xfff0 # complete address for ROS
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LTOC(r3,ipl_cb,data) # address of IPL CB pointer
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l r3,0(r3) # address of IPL CB
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mtspr lr,r8 # load up the lr with warm ipl addr
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br # branch to ROS ipl
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S_EPILOG
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##page;
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##print(off);
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include(low_dsect.m4)
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include(machine.m4)
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include(systemcfg.m4)
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include(scrs.m4)
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##print(on);
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.toc
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TOCE(ipl_cb,data)
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