519 lines
24 KiB
C
519 lines
24 KiB
C
/* @(#)52 1.1 src/bos/kernel/sys/POWER/dmpauser.h, sysxdmpa, bos411, 9428A410j 4/30/93 12:34:50 */
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/*
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* COMPONENT_NAME: (MPAINC) MP/A HEADER FILES
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*
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* FUNCTIONS:
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*
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* ORIGINS: 27
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*
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* IBM CONFIDENTIAL -- (IBM Confidential Restricted when
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* combined with the aggregated modules for this product)
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* SOURCE MATERIALS
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*
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* (C) COPYRIGHT International Business Machines Corp. 1993
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* All Rights Reserved
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* US Government Users Restricted Rights - Use, duplication or
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* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
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*/
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#include <sys/termio.h>
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#include <sys/ioctl.h>
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#include <sys/devinfo.h>
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#include <sys/comio.h>
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#include <sys/types.h>
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#include <sys/err_rec.h>
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#define MAX_FRAME_SIZE 4096 /* Maximum SDLC frame size */
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#define MAX_CHAN 1 /* Maximum number of channels */
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/* this is not multipled device driver */
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typedef struct errmsg {
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struct err_rec0 err;
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char file[32];
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char data1[80]; /* use data1 and data2 to show detail */
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int data2; /* data in the errlog report. Define */
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/* these fields in the errlog template */
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/* These fields may not be used in all */
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/* cases. */
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} ;
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/**************************************************************************
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* MPA OPTION 1 return codes *
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**************************************************************************/
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/* Results for all the xmit commands are passed back in the Tx I/R */
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/* (xmit result irpt reg). The TIC (xmit irpt codes) are defined as */
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/* follows: */
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#define XMIT_EARLY_IRPT 12 /* Early Tx irpt */
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#define XMIT_COMPLETE 13 /* xmit done ok */
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#define XMIT_DMA_UNDERRUN 14 /* DAM underrun */
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#define XMIT_CL_TO_SEND_ERR 15 /* clear to send error, no connect */
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#define XMIT_ABORT_DONE 16 /* abort complete. */
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#define XMIT_PIO_ERROR 17 /* Pio error on xmit processing */
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/* the results for the first three receive commands are as follows: */
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/* in non_buffered mode the first byte in RxI/R reg (recv result irpt reg */
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/* is RIC (receive irpt code) then R0 and R1 (LSB and MSB of actual length */
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/* received. The high order 3 bits of the RIC are for partial bytes */
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/* received on the last byte and must be ignored when checking RIC. */
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#define RECV_GEN_OK 0 /* Gen or sel A1 match read ok. */
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#define RECV_SEL_OK 1 /* Sel read ok A2 match. */
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#define RECV_CRC_ERR 3 /* Read crc error detected */
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#define RECV_ABORTED 4 /* Read abort detected */
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#define RECV_IDLE 5 /* Idle detected on read */
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#define RECV_EOP 6 /* EOP detected on read */
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#define RECV_BAD_FRAME 7 /* frame < 32 bits */
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#define RECV_DMA_OVERRUN 8 /* dma overrun on read */
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#define RECV_MEM_OVERFLOW 9 /* memory buffer too small */
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#define RECV_CARRIER_DOWN 10 /* carrier detect failure */
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#define RECV_IRPT_OVERRUN 11 /* Receiver irpt overrun */
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#define RECV_PIO_ERROR 12 /* Pio error on recv processing */
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/* In buffered mode two more result bytes will be sent.. Addr and control */
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/* bytes will follow the RIC, R0 and R1 . */
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/**************************************************************************
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* MPA IOCTL COMMANDS *
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**************************************************************************/
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#define MPA ('m'<<8)
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#define MPA_RW_PORT (MPA|0xA1)
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#define MPA_CMD_8273 (MPA|0xA2)
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#define MPA_RW_POS (MPA|0xA3)
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#define MPA_GET_ACB (MPA|0xA4)
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/**************************************************************************
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* MPA codes returned in option[0] as ASYNC status *
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**************************************************************************/
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/**************************************************************************
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* MPA IOCTL DIAGNOSTIC/SETUP COMMANDS *
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**************************************************************************/
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/******* these defines are for trace hooks *******************/
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#define ADAPT_TOO_BIG 0x000000f0 /* adapter number is too big */
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#define NO_ACB 0x000000f1 /* acb is NULL */
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#define NO_OFFL_INTR 0x000000f2 /* there is no offlevel intr
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structure */
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#define NO_INTR_REG 0x000000f3 /* no interrupt registration */
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#define NO_PORT_DDS 0x000000f4 /* no dds for requested port */
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#define CHAN_TOO_BIG 0x000000f5 /* channel > CHAN_MAX */
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#define CHAN_BUSY 0x000000f6 /* channed is used by kernel */
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#define NO_MBUF_AVAIL 0x000000f7 /* no mbuf available */
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#define NO_XMIT_CHAIN 0x000000f8 /* no transmit chain */
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#define ADAPT_ALRDY_OPEN 0x000000f9 /* adapter already opened */
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#define UIO_MOVE_ERR 0x000000fd /* error in uiomove */
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#define PHYS_LINK_INV 0x000000e0 /* physical link is invalid */
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#define DATA_PROTO_INV 0x000000e1 /* data protocol is invalid */
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#define BAUD_RATE_INV 0x000000e2 /* baud rate is invalid */
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#define NO_ERROR 0x000000e3
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#define PARM1 0x00000001 /* parameter # 1 */
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#define PARM2 0x00000002 /* parameter # 2 */
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#define PARM3 0x00000003 /* parameter # 3 */
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#define PARM4 0x00000004 /* parameter # 4 */
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/*
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* Multi Protocol Single Port start device data structure Definition
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*/
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typedef struct
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{
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char retry_cnt;
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char rsv ;
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ushort retry_delay;
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ushort cps_group_0;
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ushort cps_group_1;
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ushort cps_group_2;
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ushort cps_group_3;
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ushort cps_group_4;
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ushort cps_group_5;
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ushort cps_group_6;
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ushort cps_group_7;
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ushort cps_group_8;
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ushort cps_group_9;
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ushort cps_netlog_0;
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ushort cps_netlog_1;
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ushort cps_netlog_2;
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ushort cps_netlog_3;
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ushort cps_netlog_4;
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ushort cps_netlog_5;
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ushort cps_netlog_6;
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ushort cps_netlog_7;
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ushort cps_netlog_8;
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ushort cps_netlog_9;
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char gr0_thresh;
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char gr1_thresh;
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char gr2_thresh;
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char gr3_thresh;
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char gr4_thresh;
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char gr5_thresh;
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char gr6_thresh;
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char gr7_thresh;
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char gr8_thresh;
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char gr9_thresh;
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ushort select_sig_len;
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char select_sig[256];
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} t_x21_data;
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typedef struct T_ERR_THRESH
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{
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ulong tx_err_thresh;
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ulong rx_err_thresh;
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ulong tx_err_percent;
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ulong rx_err_percent;
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ulong tx_underrun_thresh;
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ulong tx_cts_drop_thresh;
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ulong tx_cts_timeout_thresh;
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ulong tx_fs_timeout_thresh;
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ulong rx_overrun_err_thresh;
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ulong rx_abort_err_thresh;
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ulong rx_frame_err_thresh;
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ulong rx_par_err_thresh;
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ulong rx_bad_sync_thresh;
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ulong rx_dma_bfr_err_thresh;
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} t_err_threshold;
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typedef struct MPA_START
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{
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cio_sess_blk_t sb;
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unsigned char phys_link; /* physical link */
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unsigned char station_type; /* specify type of station */
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#define PRIMARY 0x01 /* if set use general recv */
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#define SECONDARY 0x02 /* if set use selective recv */
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unsigned char dial_proto; /* dial protocol */
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unsigned char dial_flags; /* dial protocol */
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#define ENABLE_V.25 0x10 /* enable autodial */
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#define SET_DTR 0x04 /* set DTR */
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#define SET_RTS 0x01 /* set RTS */
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unsigned char data_proto; /* protocol in data transfer */
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#define SDLC 0x01
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#define BI_SYNC 0x02
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#define ASYNC 0x04
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unsigned char data_flags; /* protocol flags for data */
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#define SET_NRZI_DATA 0x01 /* Parameter to set NZRI encoded data */
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#define SET_CLOCK_LOOPBACK 0x02 /* Parameter to set clock loopback */
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#define SET_DATA_LOOPBACK 0x04 /* Parameter to set data loopback */
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/* serial i/o mode reg */
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unsigned char modem_flags; /* modem flags sets 8255 Port C */
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/**************************************************************************
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* MPA 8255 PORT_C values. Defined for internal control functions *
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* and to monitor receive data. *
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* When the bit must be set to one or in the defined value. *
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* When the bit must be set to 0 and in the defined value. *
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* Bits pc0-pc3 are read/write and bits pc4-pc7 are read only. *
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* NOTE: using intel notation ordered as pc7-pc0. *
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**************************************************************************/
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/* writeable*/
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#define GATE_INT_CLK 0x01 /* 1 = Gate internal clock */
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#define GATE_EXT_CLK 0x02 /* 1 = Gate external clock */
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#define ELECTRONIC_WRAP 0x04 /* 1 = Electronic wrap */
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#define NO_IRPTS 0x08 /* disable irpts and dma when set */
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/* read only */
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#define RECV_DATA 0x10 /* Oscillating = receiving data */
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#define TIMER0_OUT 0x20 /* Oscillating = timer 0 output */
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#define TEST_ACTIVE 0x40 /* 0 = Test actvie in elec wrap */
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#define SDLC_BSC 0x80 /* 1 = SDLC, 0 = BSC adapter */
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unsigned char port_b_8255; /* modem flags sets 8255 Port B */
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/**************************************************************************
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* MPA 8255 PORT_B values. Used for modem control. *
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* When the bit must be set to one or in the defined value. *
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* When the bit must be set to 0 and in the defined value. *
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* This is a read/write port. *
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**************************************************************************/
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#define SPEED_SEL_OFF 0x01 /* 0 = Turn on speed select */
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#define SEL_STANBY_OFF 0x02 /* 0 = Turn on Select Standby */
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#define TEST_OFF 0x04 /* 0 = Turn on test */
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#define FREE_STAT_CHG 0x08 /* 0 = Reset modem status changed logic */
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#define RESET_8273 0x10 /* 1 = Reset the 8273 */
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#define GATE_TIMER2 0x20 /* 1 = Gate timer 2 */
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#define GATE_TIMER1 0x40 /* 1 = Gate timer 1 */
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#define ENABLE_IRPT4 0x80 /* 1 = Enable irpt level 4 */
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unsigned char poll_addr; /* poll address */
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unsigned char select_addr; /* select address */
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unsigned char select_cntl; /* select control */
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unsigned char modem_intr_mask; /* currently unused */
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unsigned short baud_rate; /* baud rate for internal clk */
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unsigned short rcv_timeout; /* receive time out */
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unsigned short rcv_data_offset; /* receive data offset */
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unsigned short dial_data_length; /* length of dial data */
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unsigned char mode_reg_flags; /* 8273 mode reg flags */
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#define SET_FLAG_STREAM 0x01 /* Parameter to set flag stream mode */
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#define SET_PRE_FRAME_MODE 0x02 /* Parameter to set pre_frame sync mode */
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#define SET_BUFFERED_MODE 0x04 /* Parameter to set buffered mode. */
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#define SET_EARLY_TX_ON 0x08 /* Parameter to set early xmit irpt on */
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#define SET_EOP_IRPT_ON 0x10 /* Parameter to set end of poll irpt on */
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#define SET_HDLC_ABORT 0x20 /* Parameter to set HDLC abort */
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unsigned char xfer_mode; /* 8273 xfer mode reg */
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#define SET_NO_DMA 0x01 /* Parameter to set irpt xfer mode */
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unsigned char bit_delay; /* 8273 one bit delay mode setting */
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#define SET_1_BIT_DELAY 0x80 /* Parameter to set 1 bit delay */
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unsigned char diag_flags; /* flags for various diagnostics */
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#define XMIT_ONLY 0x01 /* when set no recv command will be issued */
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union
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{
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t_x21_data *p_x21_data;
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char (*p_dial_data) [256];
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} t_dial_data;
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t_err_threshold *p_err_threshold;
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} mpa_start_t ;
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typedef struct T_ERR_LOG
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{
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unsigned error_id;
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char resource_name[8];
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char detail_data[64]; /* detail data of error */
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} t_error_log;
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typedef struct mp_write_extension
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{
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struct write_extension cio_ext; /* COMIO write extension */
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uchar transparent; /* bisync transparent mode flag */
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uchar adr;
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uchar cntl;
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} t_write_ext;
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/******************************************************************************
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* MSQP card register state structure. *
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***************************************************************************/
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typedef struct Q_STATE
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{
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uchar port_a_8255;
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uchar port_b_8255;
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uchar port_c_8255;
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uchar mode_sel_8255;
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int cnt_0_8254; /* not used */
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int cnt_1_8254; /* not used */
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int cnt_2_8254; /* not used */
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uchar statreg_8273;
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uchar resreg_8273;
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uchar tx_ir_8273;
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uchar rx_ir_8273;
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uchar port_a_8273;
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uchar port_b_8273;
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uchar oper_mode_8273; /* these last fout regs are internal to */
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uchar serial_io_8273; /* 8273 and can't be read, so I set up */
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uchar one_bit_8273; /* these values as I set up these regs */
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uchar data_xfer_8273;
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} card_state_t;
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/*
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** Device-specific statistics
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** Returned in driver statistics structure.
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*/
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typedef struct mpa_stats {
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ulong sta_que_overflow; /* status lost, full status que */
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ulong recv_lost_data; /* receive packet lost*/
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ulong total_intr; /* total interrupts */
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ulong recv_not_handled; /* interrupts not handled, */
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ulong xmit_not_handled; /* interrupts not handled, */
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ulong recv_irpt_error; /* interrupts with no results */
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ulong xmit_irpt_error; /* interrupts with no results */
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ulong recv_intr_cnt; /* number of receive interrupts */
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ulong xmit_intr_cnt; /* number of transmit interrupts */
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ulong rec_no_mbuf; /* no mbuf available */
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ulong xmit_sent; /* transmit commands send to MPA */
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ulong xmit_dma_completes; /* transmit dma transfers completed */
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ulong recv_sent; /* receive dma transfers completed */
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ulong recv_dma_completes; /* receive dma transfers completed */
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ulong recv_crc_errors;
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ulong recv_aborts;
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ulong recv_idle_detects;
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ulong recv_eop_detects;
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ulong recv_frame_to_small;
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ulong recv_dma_overruns;
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ulong recv_buf_overflow;
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ulong recv_cd_failure;
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ulong recv_irpt_overruns;
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ulong xmit_early_irpts;
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ulong xmit_completes;
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ulong xmit_dma_underrun;
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ulong xmit_cts_errors;
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ulong xmit_aborts;
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ulong recv_completes;
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ulong io_irpt_error;
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int bps_rate;
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ulong recv_pio_byte;
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ulong xmit_pio_byte;
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ulong irpt_fail;
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ulong irpt_succ;
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} mpa_stats_t;
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/*
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** Driver statistics structure.
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** Returned by CIO_QUERY ioctl operation
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*/
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typedef struct QUERY {
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cio_stats_t cc; /* General COMIO statistics */
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mpa_stats_t ds; /* Device specific statistics */
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} mpa_query_t;
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typedef struct rw_port
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{
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int port_addr; /* i/o addr index to the desired port */
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uchar rw_flag; /* in - destination buffer pointer */
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#define MPA_WRITE 0x01
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#define MPA_READ 0x02
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uchar value; /* value to write or value read */
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} rw_port_t;
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typedef struct COMMAND {
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uchar cmd;
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uchar parm[3];
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int parm_count;
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uchar flag;
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#define RETURN_RESULT 0x01 /* Set if result expected. */
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uchar result;
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} cmd_phase_t;
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typedef struct FRAME {
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uchar addr;
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uchar cntl;
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uchar data[MAX_FRAME_SIZE - 2];
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} frame_t;
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/*************************************************************************
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* I/O Register Offsets from start of I/O Memory base address *
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* and the defined values for each register or port *
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***********************************************************************/
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#define PORT_A_8255 0x00 /* 8255 Port A Select offset */
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#define PORT_B_8255 0x01 /* 8255 Port B Select offset */
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#define PORT_C_8255 0x02 /* 8255 Port C Select offset */
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#define MODE_OFFSET 0x03 /* 8255 Mode Select offset */
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#define COUNT0_OFFSET 0x04 /* 8254 Counter0 Select */
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#define COUNT1_OFFSET 0x05 /* 8254 Counter1 Select */
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#define COUNT2_OFFSET 0x06 /* 8254 Counter2 Select */
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#define CONTROL_OFFSET 0x07 /* 8254 Control Select */
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#define WR_CMD_OFFSET 0x08 /* 8273 output command reg */
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#define RD_STAT_OFFSET 0x08 /* 8273 input status reg */
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#define WR_PARM_OFFSET 0x09 /* 8273 output parameter */
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#define RD_RES_OFFSET 0x09 /* 8273 input result */
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#define WR_TEST_OFFSET 0x0A /* 8273 output test mode */
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#define RD_TX_IR_OFFSET 0x0A /* 8273 input xmit irpt result */
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#define RD_RX_IR_OFFSET 0x0B /* 8273 input recv irpt result */
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#define WR_DATA_OFFSET 0x0C /* 8273 output data reg */
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#define RD_DATA_OFFSET 0x0C /* 8273 input data reg */
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/*************************************************************************
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* MPA 8255 PORT_A values. Used for sensing external modem signals *
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* and internal signals. The 8273 has commands for reading this reg. *
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* When checking bit values, if 0 indicates the condition, negate the *
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* if statement. example if( !(reg_val & RING_ON) ) { ring is on } *
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* This is a read only port. *
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*************************************************************************/
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#define RING_ON 0x01 /* 0 = Ring indicator on */
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#define CARRIER_DET 0x02 /* 0 = Data carrier detect on */
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#define XMIT_CLK_ON 0x04 /* 1 = on , 0 = off */
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#define CLEAR_TO_SEND 0x08 /* 0 = Clear to send on */
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#define RECV_CLK_ON 0x10 /* 1 = on , 0 = off */
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#define MODEM_STAT_CHG 0x20 /* 1 = Modem status changed */
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#define TIMER2_ACTIVE 0x40 /* 1 = Timer 2 output active */
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#define TIMER1_ACTIVE 0x80 /* 1 = Timer 1 output active */
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#define TIMER_ACTIVE 0xC0 /* Either timer active */
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#define SET_8255_MODE 0x98 /* Set up mode for 8255 */
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/***************************************************************************
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* Currently no defines for the 8254 counter hardware *
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***************************************************************************/
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/***************************************************************************
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* This next section contains the definitions of the various commands *
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* and the parameters that must be passed with the commands and the *
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* results passed back during the result phase. *
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***************************************************************************/
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/***************************************************************************
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* Initialization/Configuration commands and parameters *
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* There are no results for these commands. *
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***************************************************************************/
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#define SET_1_BIT_DELAY_CMD 0xA4 /* cmd to set up one bit delay mode */
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#define RESET_1_BIT_DELAY_CMD 0x64 /* cmd to reset up one bit delay mode */
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#define RESET_1_BIT_DELAY 0x7F /* parameter to reset 1 bit delay */
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#define SET_DATA_XFER_CMD 0x97 /* cmd to set data xfer mode */
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/* NOTE: use this reset command with reset mask to set up for dma adapter */
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#define RESET_DATA_XFER_CMD 0x57 /* cmd to reset data xfer mode */
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#define RESET_TO_USE_DMA 0xFE /* Parameter to set up dma xfer mode */
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#define SET_OPER_MODE_CMD 0x91 /* cmd to set operating mode reg */
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#define RESET_OPER_MODE_CMD 0x51 /* cmd to reset operating mode reg */
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#define RESET_FLAG_STREAM 0xFE /* Parameter to reset flag stream mode */
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#define RESET_PRE_FRAME_MODE 0xFD /* Parameter to reset pre_frame sync mode */
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#define RESET_BUFFERED_MODE 0xFB /* Parameter to reset buffered mode. */
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#define RESET_EARLY_TX_ON 0xF7 /* Parameter to reset early xmit irpt on */
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#define RESET_EOP_IRPT_ON 0xEF /* Parameter to reset end of poll irpt on */
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#define RESET_HDLC_ABORT 0xDF /* Parameter to reset HDLC abort */
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#define SET_IO_MODE_CMD 0xA0 /* cmd to set serial io mode reg */
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#define RESET_IO_MODE_CMD 0x60 /* cmd to reset serial io mode reg */
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#define RESET_NZRI_DATA 0xFE /* Parameter to reset NZRI encoded data */
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#define RESET_CLOCK_LOOPBACK 0xFD /* Parameter to reset clock loopback */
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#define RESET_DATA_LOOPBACK 0xFB /* Parameter to reset data loopback */
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/***************************************************************************
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* Reset command no parms and no results. The reset is accomplished *
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* outside the normal command interface by writing a 0x01 to the address *
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* WR_TEST_OFFSET then waiting 10 cycles and writing 0x00. *
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***************************************************************************/
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#define START_RESET 0x01 /* start the reset process */
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#define END_RESET 0x00 /* end the reset process */
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/***************************************************************************
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* modem control commands parms and results *
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* 8273 PORT A is read only, PORT B is read/write *
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***************************************************************************/
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#define READ_8273_PORT_A_CMD 0x22 /* Cmd to read from 8273 Port A */
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/* no parms, result in RD_RES_OFFSET */
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#define PORT_A_8273_CTS 0x01 /* 1 = clear to send active */
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#define PORT_A_8273_CD 0x02 /* 1 = carrier detect active */
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#define PORT_A_8273_PA2 0x04 /* 1 = data set ready */
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#define PORT_A_8273_PA3 0x08 /* 1 = CTS changed */
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#define PORT_A_8273_PA4 0x10 /* 1 = DSR changed */
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#define READ_8273_PORT_B_CMD 0x23 /* Cmd to read from 8273 Port B */
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/* no parms, data in RD_RES_OFFSET */
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#define SET_8273_PORT_B_CMD 0xA3 /* Cmd to set 8273 Port B values */
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/* parameter is set_mask, no results */
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#define SET_8273_PORT_B_RTS 0x01 /* mask bit to set req to send bit */
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#define SET_8273_PORT_B_PB1 0x02 /* mask bit to set PB1 bit */
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#define SET_8273_PORT_B_PB2 0x04 /* mask bit to set Data terminal ready */
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#define SET_8273_PORT_B_PB3 0x08 /* mask bit to set PB3 bit */
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#define SET_8273_PORT_B_PB4 0x10 /* mask bit to set V.25 enable bit */
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#define SET_8273_PORT_B_PB5 0x20 /* mask bit to set flag detect bit */
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#define RESET_8273_PORT_B_CMD 0x63 /* Cmd to reset 8273 Port B values */
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/* parameter reset_mask, no results */
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#define RESET_8273_PORT_B_RTS 0xFE /* mask bit to reset req to send bit */
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#define RESET_8273_PORT_B_PB1 0xFD /* mask bit to reset PB1 bit */
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#define RESET_8273_PORT_B_PB2 0xFB /* mask bit to reset Data terminal ready */
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#define RESET_8273_PORT_B_PB3 0xF7 /* mask bit to reset PB3 bit */
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#define RESET_8273_PORT_B_PB4 0xEF /* mask bit to reset V.25 enable bit */
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#define RESET_8273_PORT_B_PB5 0xDF /* mask bit to reset flag detect bit */
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