325 lines
12 KiB
C
325 lines
12 KiB
C
/* @(#)73 1.17.1.9 src/bos/kernel/sys/POWER/iocc.h, sysios, bos41B, 412_41B_sync 1/6/95 13:15:02 */
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/*
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* COMPONENT_NAME: (SYSIOS) IO Channel Converter Harware Definitions
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*
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* FUNCTIONS:
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*
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* ORIGINS: 27, 83
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*
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* (C) COPYRIGHT International Business Machines Corp. 1988, 1994
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* All Rights Reserved
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* Licensed Materials - Property of IBM
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*
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* US Government Users Restricted Rights - Use, duplication or
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* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
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*/
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/*
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* LEVEL 1, 5 Years Bull Confidential Information
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*/
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#ifndef _H_IOCC
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#define _H_IOCC
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#ifndef _H_TYPES
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#include <sys/types.h>
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#endif /* _H_TYPES */
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/*
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* Bit definitions that are common to all architectures and implementations
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* unless otherwise noted.
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*/
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/*
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* Interrupt Request Register - int_request
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*/
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#define IRR_MISC 0x80000000 /* miscellaneous interrupt */
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#define IRR_KBD 0x40000000 /* keyboard interrupt */
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#define IRR_SERIAL 0x20000000 /* serial port interrupt */
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#define IRR_CHECK_F1 0x00800000 /* RESERVED(old PC AT channel check) */
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#define IRR_PARALLEL 0x00040000 /* parallel port interrupt */
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/*
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* Miscellaneous Interrupt Register - int_misc
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*/
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#define IMI_CHANCK 0x80000000 /* channel check */
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#define IMI_TIMEOUT 0x40000000 /* bus timeout */
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#define IMI_KBDEXT 0x20000000 /* ctl-alt key sequence (PWR)*/
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#define IMI_BUMP 0x20000000 /* Service processor interrupt (PPC)*/
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/*
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* This is the main IOCC register file mapping for the POWER architecture.
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* Accesses must be done with the IOCC register file access bit set in
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* the segreg. See IOCCACC in sys/ioacc.h.
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*/
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#define IOCC0_BID 0x820C00E0 /* IOCC 0 segment register value */
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#define IOCC1_BID 0x821C00E0 /* IOCC 1 segment register value */
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#define IOCC2_BID 0x821C00E0 /* IOCC 2 segment register value */
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#define IOCC3_BID 0x821C00E0 /* IOCC 3 segment register value */
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#define IOCC_BID IOCC0_BID /* From when there was only 1 IOCC */
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#define IO_IOCC 0x00400000 /* base address of register file */
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struct iocc /* interrupt handler structure */
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{
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char reserved1[16]; /* reserved */
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unsigned long config; /* IOCC config register */
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#define ICF_ENABLE 0x80000000 /* master enable */
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/* bits 2-3=0->finish cycle(burst)*/
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#define ICF_BURST16 0x10000000 /* burst control - 1.6us */
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#define ICF_BURST32 0x20000000 /* burst control - 3.2us */
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#define ICF_BURST64 0x30000000 /* burst control - 6.4us */
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#define ICF_DISCK 0x08000000 /* disable CHCK on parity error */
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#define ICF_DISSD 0x04000000 /* disable streaming data protocol */
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/* bits 6-7 = 0 -> disable refresh */
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#define ICF_REFR60 0x01000000 /* refresh rate 60us */
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#define ICF_REFR30 0x02000000 /* refresh rate 30us */
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#define ICF_REFR15 0x03000000 /* refresh rate 15us */
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/* 128K RAM bits 9-11 = 0 */
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#define ICF_RAM256K 0x00100000 /* 256K RAM on IOCC */
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#define ICF_RAM512K 0x00200000 /* 512K RAM on IOCC */
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#define ICF_RAM1M 0x00300000 /* 1M RAM on IOCC */
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#define ICF_RAM2M 0x00400000 /* 2M RAM on IOCC */
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#define ICF_RAM4M 0x00500000 /* 4M RAM on IOCC */
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#define ICF_RAM8M 0x00600000 /* 8M RAM on IOCC */
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#define ICF_RAM16M 0x00700000 /* 16M RAM on IOCC */
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#define ICF_RAM_MASK 0x00700000 /* mask for RAM bits */
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#define ICF_RAM_SHIFT 20 /* shift for RAM bits */
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/* arb time = 100ns bits12-15=0 */
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/* ((bits12-15)+1)*100 = arbt in ns*/
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#define ICF_ARB200 0x00010000 /* arbitration time = 200ns */
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#define ICF_ARB300 0x00020000 /* arbitration time = 300ns */
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#define ICF_ARB1600 0x000F0000 /* arbitration time = 1600ns */
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#define ICF_DUAL_BUF 0x00000080 /* set if dual buffer support */
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#define ICF_SLAVE_TCW 0x00000040 /* mask for slave with TCWs */
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#define ICF_BUF_MSK 0x00000030 /* mask for buffer/coherency */
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#define ICF_SLVCHN_MSK 0x0000000F /* number of DMA slave channels */
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char reserved2[12]; /* reserved */
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unsigned long bus_status; /* bus status register */
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char reserved3[8]; /* reserved */
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unsigned long c_reset_reg; /* component reset register */
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char reserved4[16]; /* reserved */
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unsigned long limit; /* l/st limit register */
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char reserved[28]; /* reserved */
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char reserved_dma[32]; /* dma register address space */
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unsigned long int_enable; /* interrupt enable reg */
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unsigned long int_request; /* interrupt request reg */
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unsigned long int_misc; /* misc interrupt reg */
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unsigned long rfi; /* return from interrupt */
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unsigned long vector[4]; /* interrupt vector table */
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};
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/*
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* The following can be used to convert the iocc.config value into
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* the number of TCWs supported on this machine.
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*/
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#define ICF_TCWS(c) ( ((c) & ICF_SLAVE_TCW) ? \
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((0x8000 << (((c) & ICF_RAM_MASK) >> ICF_RAM_SHIFT)) >> 2) : \
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(((0x20000 << (((c) & ICF_RAM_MASK) >> ICF_RAM_SHIFT)) >> 2) - 0x2000))
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#define ICF_SLV_TCWS(c) (((c) & ICF_SLAVE_TCW) ? (256*ICF_NUM_SLVCHN(c)) : 0)
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#define ICF_NUM_TCWS(c) (ICF_TCWS(c) - ICF_SLV_TCWS(c))
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/*
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* The following can be used to check for bufferd IOCCs
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*/
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#define ICF_BUFFERED(c) \
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(((c) & ICF_BUF_MSK) != 0x00000010)
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/*
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* The following can be used to convert the iocc.config value to the number
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* of slave channeds supported
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*/
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#define ICF_NUM_SLVCHN(c) \
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((((c) & ICF_SLVCHN_MSK) == 0) ? 0xF : (c) & ICF_SLVCHN_MSK)
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/*
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* Address of the IOCC delay command. For delay use store byte to
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* IOCC_DELAY + (number of micro seconds - 1)
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*/
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#define IOCC_DELAY 0xE0
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/*
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* This is the card config register.
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* It is 2 words long, with support for up to 16 cards.
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* Accesses to the card config reg are 8-bits at a time, and must
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* be done with the IOCC register file access bit set in the segreg.
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* (> 8 bit accesses may be done from the CPU; however the IOCC
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* will break them down).
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*/
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#define IO_CONFIG 0x00400000 /* offset into IOCC of card config */
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#define IO_CONFIG_SLOT 0x000F0000 /* slot select for card config */
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struct card_config /* card config data */
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{
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char card_idL; /* card id - low byte */
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char card_idM; /* card id - high byte */
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char dev1; /* device specific */
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char dev2; /* device specific */
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char dev3; /* device specific */
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char dev4; /* device specific */
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char subaddr1; /* sub-addressing */
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char subaddr2; /* sub-addressing */
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};
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/*
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* The Micro Channel to PC AT bus converter is accessed as a
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* card configuration register.
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*/
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#define F1_CONFIG 0x00470000 /* base address */
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#define f1_modes dev1 /* converter modes */
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#define F1_DIAG 0x02 /* diagnostic mode */
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#define F1_ENABLE 0x01 /* converter enable */
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#define f1_dmamask dev2 /* DMA channel masks */
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#define f1_dmafair dev3 /* DMA fairness */
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#define f1_eoi dev4 /* end of interrupt */
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#define F1_CCK 0x80 /* convert parity error */
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#define f1_intmaskH subaddr2 /* mask bus lvls 15-8 */
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#define f1_intmaskL subaddr1 /* mask bus lvls 7-0 */
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/*
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* Labels used for the power status register
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* in the IOCC.
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*/
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#define EPOW_MASK 0xF0000000 /* mask off all but EPOW bits */
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#define PSR_ADDRESS 0x004000E4 /* address of power status register */
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#define PCRR_ADDRESS 0x004000E8 /* addr of power ctrl reset register */
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#define NORMAL_STATE 0x00000000 /* normal state for power supply */
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#define BATTERY 0x10000000 /* running on battery bit of PSR */
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#define LOPP 0x80000000 /* loss of Primary Power */
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#define THERMAL_WARNING 0x50000000 /* abnormally high temperature */
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#define PWR_OVERLOAD 0x70000000 /* power supply overload */
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#define PWR_FAN_FAULT 0x90000000 /* power supply fan failure */
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#define KEY_POS_MASK 0x00000003 /* mask off all but key position bits */
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#define KEY_POS_NORMAL 0x03 /* key is in the normal position */
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#define KEY_POS_SECURE 0x01 /* key is in the secure position */
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#define KEY_POS_SERVICE 0x02 /* key is in the service position */
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#define BEHAVIOR_SHIFT 18 /* behavior bits are bits 10-13 */
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#define BEHAVIOR_MASK 0xF /* mask off all but behavior bits */
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#define USE_EPOW_BITS 0x0 /* interpret bits 0-9 of PKSR */
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#define WARN_COOLING 0x1 /* no action "warning cooling problem"*/
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#define WARN_POWER 0x2 /* no action "warning power problem" */
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#define SLOW_SHUTDOWN 0x3 /* 10 minutes to shut down */
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#define FAST_SHUTDOWN 0x4 /* 20 seconds to shut down */
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#define IMMED_SHUTDOWN 0x5 /* immediate power down condition */
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#define IMMEDX_SHUTDOWN 0x6 /* immediate power down for expansion */
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/*
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* Labels define the range of addresses that contain iocc commands
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* and control registers
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*/
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#define IOCC_COMMAND_START 0x00400000
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#define IOCC_COMMAND_END 0x004fffff
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/*
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* IOCC segment register bits
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*/
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#define IOCCSR_KEY 0x40000000 /* Privlege key */
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#define IOCCSR_SELECT 0x00000080 /* IOCC space select */
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/* ----------------------------------------------------------------------- */
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/*
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* This is the main IOCC register file mapping for the PowerPC architecture.
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* Accesses must be done with the IOCC register file access bit set in
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* the segreg. See IOCCACC in sys/ioacc.h.
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*/
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/*
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* PowerPC IOCC definitions and macros
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*/
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#define IOCC_SEGREG 0x80000000 /* IOCC segment register value */
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#define IO_IOCC_PPC 0x10000 /* base address of IOCC space */
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#define IOCC_CFG_REG 0x80 /* offset to config register */
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#define IOCC_TCE_ADDR 0x9C /* offset to TCE Anchor (32-bit) */
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#define MAX_NUM_IOCCS 2 /* maximum supported IOCCs */
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/*
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* PowerPC IOCC Implementations
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*/
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#define IOCC_601_BOX 0x300000 /* device id of 601 box IOCC */
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/*
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* BUID definitions and macros
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*/
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#define BUID_SEGREG_MASK 0x1FF00000
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#define BUID_TO_IOCC( Buid ) ( IOCC_SEGREG | (uint)((uint)Buid << 20))
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/*
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* Extract Number of TCEs
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* Note: This is the TOTAL number of TCE's for this IOCC.
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* For calculation of the number of DMA Master TCE's, the TCEs
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* reserved for DMA Slave devices must be subtracted from
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* this total.
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*
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* c = contents of the TCE Address Register
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*/
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#define NUM_TCES_PPC(c) ( 0x2000 << ((c) & 0x7))
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/*
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* Extract Number of Slave Channels
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*
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* c = contents of the IOCC Config Register
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*/
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#define NUM_SLVCHN_PPC(c) ((c) & 0xF)
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/*
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* Compute the Number of Slave TCEs
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*
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* c = contents of the IOCC Config Register
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*/
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#define SLV_TCES_PPC(c) (256 * NUM_SLVCHN_PPC(c))
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struct iocc_ppc {
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char reserved1[128]; /* 0-7F, reserved */
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ulong config; /* 80, iocc config register */
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#define ICF_ENABLE 0x80000000 /* master enable */
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#define ICF_64_bit 0x80 /* 64-bit enable */
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#define ICF_MAXTCE_MSK 0x70 /* mask for max TCEs */
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ulong reserved2; /* 84, reserved */
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ulong personalized; /* 88, iocc personalization */
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ulong reserved3; /* 8C, reserved */
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ulong bus_status; /* 90, iocc bus status */
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ulong reserved4; /* 94, reserved */
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ulong tce_addr_high; /* 98, MSW of tceaddr */
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ulong tce_addr_low; /* 9C, LSW of tceaddr */
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ulong c_reset_reg; /* A0, Component reset reg */
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ulong reserved5; /* A4, reserved */
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ulong bus_map_reg; /* A8, Bus mapping register */
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char reserved6[212]; /* AC-17F, reserved */
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ulong int_enable; /* 180, interrupt enable */
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ulong reserved7; /* 184, reserved */
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ulong int_request; /* 188, interrupt request reg */
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ulong reserved8; /* 18C, reserved */
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ulong int_misc; /* 190, misc interrupt reg */
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char reserved9[44]; /* 194-1BF, reserved */
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ulong avail_procs[8]; /* 1C0-1DC, available procs */
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char reserved10[32]; /* 1E0-1FF, reserved */
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ulong xivr[16]; /* 200-23C, external intr vec */
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char reserved11[320]; /* 240-37F, reserved */
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ulong dma_slv_cntrl[8]; /* 380-39C, slave control regs*/
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char reserved12[96]; /* 3A0-3FF, reserved */
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ulong csr[16]; /* 400-43C, channel stat regs*/
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char reserved13[64]; /* 340-37F, reserved */
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ulong eoi[16]; /* 480-4BC, external intr vec */
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char reserved14[64]; /* 4C0-4FF, reserved */
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ulong ed_arblvl[16]; /* 500-53C, channel arb level en/dis */
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};
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#endif /* _H_IOCC */
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