472 lines
26 KiB
C
472 lines
26 KiB
C
/* @(#)48 1.6 src/bos/kernel/sys/POWER/mpadefs.h, mpainc, bos411, 9435C411a 8/31/94 19:01:52 */
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/*
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* COMPONENT_NAME: (MPAINC) MP/A HEADER FILES
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*
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* FUNCTIONS: COPYIN
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* COPYOUT
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* DISABLE_INTERRUPTS
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* ENABLE_INTERRUPTS
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* KFREE
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* KMALLOC
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* MPATRACE1
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* MPATRACE2
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* MPATRACE3
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* MPATRACE4
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* M_INPAGE
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* PIO_GETC
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* PIO_PUTC
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* SLEEP
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* WAKEUP
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*
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*
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* ORIGINS: 27
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*
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* IBM CONFIDENTIAL -- (IBM Confidential Restricted when
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* combined with the aggregated modules for this product)
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* SOURCE MATERIALS
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*
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* (C) COPYRIGHT International Business Machines Corp. 1993
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* All Rights Reserved
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* US Government Users Restricted Rights - Use, duplication or
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* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
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*/
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/*
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*
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*/
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/*************************************************************************
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* Multi Protocol Single Port Device Driver Defines *
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************************************************************************/
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#define ACMD_ACQ (unsigned short)0
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#define MAX_ADAPTERS 2 /* number of adapters supported */
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#define MPA_MAX_OPENS 1
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#define Q_CMD_TIMEOUT 100000 /* 100000 microseconds (100 ms) */
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#define LOOP_CNTR 300
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#define DL_DELAY_REG 0xE0
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#define POS0 0x100 /* POS Register 0 IOCC offset */
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#define P0_F 0xFF /* POS Card ID low, MPA */
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#define POS1 0x101 /* POS Register 1 IOCC offset */
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#define P1_F 0xDE /* POS1 Card ID high, MPA */
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#define POS2 0x102 /* POS Register 2 IOCC offset */
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#define P2_ENABLE 0x01 /* -sleep/+ENABLE */
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#define P2_SDLC_MODE 0x10 /* Set SDLC mode */
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#define P2_ALT_SDLC 0x12 /* Set alternate SDLC mode */
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#define P2_DMA_ENABLED 0x20 /* Set if dma enabled for SDLC mode*/
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#define P2_NOT_V25 0x40 /* 0 if V.25 bis exits*/
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#define POS3 0x103 /* POS Register 3 IOCC offset */
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#define P3_ARB_1 0x01 /* arb level for SDLC */
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#define P3_ARB_7 0x07 /* arb level for ALT SDLC */
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#define MAX_FRAME_SIZE 4096 /* Maximum SDLC frame size */
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#define MAX_XMITS 7 /* Maximum SDLC xmits before poll/final bit */
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#define POLL_BIT_OFFSET 1 /* Offset for poll/final bit */
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#define POLL_BIT 0x10 /* Poll/Final Bit mask */
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#define GENERAL 0x01 /* if set use general recv */
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#define SELECTIVE 0x02 /* if set use selective recv */
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#define BROADCAST_ADDR 0xFF /* secondary "broadcast" address */
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#define ENABLE_V.25 0x10 /* enable autodial */
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#define SET_DTR 0x04 /* set DTR */
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#define SET_RTS 0x01 /* set RTS */
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#define SET_NRZI_DATA 0x01 /* Parameter to set NZRI encoded data */
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#define SET_CLOCK_LOOPBACK 0x02 /* Parameter to set clock loopback */
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#define SET_DATA_LOOPBACK 0x04 /* Parameter to set data loopback */
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/**************************************************************************
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* MPA 8255 PORT_C values. Defined for internal control functions *
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* and to monitor receive data. *
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* When the bit must be set to one or in the defined value. *
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* When the bit must be set to 0 and in the defined value. *
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* Bits pc0-pc3 are read/write and bits pc4-pc7 are read only. *
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* NOTE: using intel notation ordered as pc7-pc0. *
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**************************************************************************/
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/* writeable*/
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#define GATE_INT_CLK 0x01 /* 1 = Gate internal clock */
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#define GATE_EXT_CLK 0x02 /* 1 = Gate external clock */
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#define ELECTRONIC_WRAP 0x04 /* 1 = Electronic wrap */
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#define NO_IRPTS 0x08 /* disable irpts and dma when set */
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/* read only */
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#define RECV_DATA 0x10 /* Oscillating = receiving data */
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#define TIMER0_OUT 0x20 /* Oscillating = timer 0 output */
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#define TEST_ACTIVE 0x40 /* 0 = Test actvie in elec wrap */
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#define SDLC_BSC 0x80 /* 1 = SDLC, 0 = BSC adapter */
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/**************************************************************************
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* MPA 8255 PORT_B values. Used for modem control. *
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* When the bit must be set to one or in the defined value. *
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* When the bit must be set to 0 and in the defined value. *
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* This is a read/write port. *
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**************************************************************************/
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#define SPEED_SEL_OFF 0x01 /* 0 = Turn on speed select */
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#define SEL_STANBY_OFF 0x02 /* 0 = Turn on Select Standby */
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#define TEST_OFF 0x04 /* 0 = Turn on test */
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#define FREE_STAT_CHG 0x08 /* 0 = Reset modem status changed logic */
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#define RESET_8273 0x10 /* 1 = Reset the 8273 */
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#define GATE_TIMER2 0x20 /* 1 = Gate timer 2 */
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#define GATE_TIMER1 0x40 /* 1 = Gate timer 1 */
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#define ENABLE_IRPT4 0x80 /* 1 = Enable irpt level 4 */
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/**************************************************************************
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* MPA OPTION 1 return codes *
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**************************************************************************/
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/* Results for all the xmit commands are passed back in the Tx I/R */
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/* (xmit result irpt reg). The TIC (xmit irpt codes) are defined as */
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/* follows: */
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#define XMIT_EARLY_IRPT 12 /* Early Tx irpt */
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#define XMIT_COMPLETE 13 /* xmit done ok */
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#define XMIT_DMA_UNDERRUN 14 /* DAM underrun */
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#define XMIT_CL_TO_SEND_ERR 15 /* clear to send error, no connect */
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#define XMIT_ABORT_DONE 16 /* abort complete. */
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#define XMIT_PIO_ERROR 17 /* Pio error on xmit processing */
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/* the results for the first three receive commands are as follows: */
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/* in non_buffered mode the first byte in RxI/R reg (recv result irpt reg */
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/* is RIC (receive irpt code) then R0 and R1 (LSB and MSB of actual length */
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/* received. The high order 3 bits of the RIC are for partial bytes */
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/* received on the last byte and must be ignored when checking RIC. */
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#define RECV_GEN_OK 0 /* Gen or sel A1 match read ok. */
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#define RECV_SEL_OK 1 /* Sel read ok A2 match. */
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#define RECV_CRC_ERR 3 /* Read crc error detected */
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#define RECV_ABORTED 4 /* Read abort detected */
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#define RECV_IDLE 5 /* Idle detected on read */
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#define RECV_EOP 6 /* EOP detected on read */
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#define RECV_BAD_FRAME 7 /* frame < 32 bits */
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#define RECV_DMA_OVERRUN 8 /* dma overrun on read */
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#define RECV_MEM_OVERFLOW 9 /* memory buffer too small */
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#define RECV_CARRIER_DOWN 10 /* carrier detect failure */
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#define RECV_IRPT_OVERRUN 11 /* Receiver irpt overrun */
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#define RECV_PIO_ERROR 12 /* Pio error on recv processing */
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/* trace hook for mpa sdlc driver */
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#ifndef HKWD_DD_MPADD
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#define HKWD_DD_MPADD 0x22c00000
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#endif
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#ifndef DD_MPA_HOOK
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#define DD_MPA_HOOK 0x21
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#endif
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#ifndef MPA_RECV_DATA
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#define MPA_RECV_DATA 0xC1
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#endif
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#ifndef MPA_XMIT_DATA
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#define MPA_XMIT_DATA 0xC2
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#endif
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/* end of trace hook for mpa sdlc driver */
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/* error ids for mpa sdlc driver */
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#ifndef ERRID_MPA_ADPERR
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#define ERRID_MPA_ADPERR 0x1a7039df /* MP/A Adapter Error */
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#endif
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#ifndef ERRID_MPA_XFTO
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#define ERRID_MPA_XFTO 0x963defb4 /* Failsafe Transmit Timer */
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#endif
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#ifndef ERRID_MPA_DSRON
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#define ERRID_MPA_DSRON 0xc8620de8 /* DSR Already On for Switched Line */
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#endif
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#ifndef ERRID_MPA_DSRDRP
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#define ERRID_MPA_DSRDRP 0x5cf8ddba /* DSR Dropped */
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#endif
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#ifndef ERRID_MPA_CTSON
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#define ERRID_MPA_CTSON 0x21db13ae /* CTS Already On at Modem */
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#endif
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#ifndef ERRID_MPA_CTSDRP
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#define ERRID_MPA_CTSDRP 0x95895e26 /* CTS Dropped During Transmit */
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#endif
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#ifndef ERRID_MPA_RCVERR
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#define ERRID_MPA_RCVERR 0xd1d9b302 /* MPA Error On Receive Data */
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#endif
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#ifndef ERRID_MPA_RCVOVR
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#define ERRID_MPA_RCVOVR 0x0590b818 /* Receive Overrun */
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#endif
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#ifndef ERRID_MPA_BFR
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#define ERRID_MPA_BFR 0xfc39cd8c /* Out of Resources */
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#endif
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#ifndef ERRID_MPA_XMTUND
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#define ERRID_MPA_XMTUND 0xc5c3e045 /* Transmit Underrun */
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#endif
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/* end of error ids for mpa sdlc driver */
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/*****************************************************************************/
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/* error threshold and trace size definitions */
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/*****************************************************************************/
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#ifdef MPA_DEBUG
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#define RX_ABORT_THRESHOLD 1
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#else
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#define RX_ABORT_THRESHOLD 5000
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#endif
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#define MPA_TRACE_SIZE (500*4) /* max number of trace table entries */
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/*****************************************************************************/
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/* internal trace routine */
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/*****************************************************************************/
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extern void mpa_trace (register uchar str[], /* trace data Footprint */
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register ulong arg2, /* trace data */
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register ulong arg3, /* trace data */
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register ulong arg4); /* trace data */
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/*****************************************************************************/
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/* tracing macros */
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/*****************************************************************************/
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#define MPATRACE1(a1) \
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mpa_trace(a1, 0, 0, 0)
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#define MPATRACE2(a1,a2) \
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mpa_trace(a1, a2, 0, 0)
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#define MPATRACE3(a1,a2,a3) \
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mpa_trace(a1, a2, a3, 0)
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#define MPATRACE4(a1,a2,a3,a4) \
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mpa_trace(a1, a2, a3, a4)
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/*************************************************************************
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* I/O Register Offsets from start of I/O Memory base address *
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* and the defined values for each register or port *
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***********************************************************************/
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#define PORT_A_8255 0x00 /* 8255 Port A Select offset */
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#define PORT_B_8255 0x01 /* 8255 Port B Select offset */
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#define PORT_C_8255 0x02 /* 8255 Port C Select offset */
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#define MODE_OFFSET 0x03 /* 8255 Mode Select offset */
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#define COUNT0_OFFSET 0x04 /* 8254 Counter0 Select */
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#define COUNT1_OFFSET 0x05 /* 8254 Counter1 Select */
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#define COUNT2_OFFSET 0x06 /* 8254 Counter2 Select */
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#define CONTROL_OFFSET 0x07 /* 8254 Control Select */
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#define WR_CMD_OFFSET 0x08 /* 8273 output command reg */
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#define RD_STAT_OFFSET 0x08 /* 8273 input status reg */
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#define WR_PARM_OFFSET 0x09 /* 8273 output parameter */
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#define RD_RES_OFFSET 0x09 /* 8273 input result */
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#define WR_TEST_OFFSET 0x0A /* 8273 output test mode */
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#define RD_TX_IR_OFFSET 0x0A /* 8273 input xmit irpt result */
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#define RD_RX_IR_OFFSET 0x0B /* 8273 input recv irpt result */
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#define WR_DATA_OFFSET 0x0C /* 8273 output data reg */
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#define RD_DATA_OFFSET 0x0C /* 8273 input data reg */
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/*************************************************************************
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* MPA 8255 PORT_A values. Used for sensing external modem signals *
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* and internal signals. The 8273 has commands for reading this reg. *
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* This is a read only port. *
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*************************************************************************/
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#define RING_OFF 0x01 /* 0 = Ring indicator on */
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#define CARRIER_DET_OFF 0x02 /* 0 = Data carrier detect on */
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#define XMIT_CLK_ON 0x04 /* 1 = on , 0 = off */
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#define CTS_OFF 0x08 /* 0 = Clear to send on */
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#define RECV_CLK_ON 0x10 /* 1 = on , 0 = off */
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#define MODEM_STAT_CHG 0x20 /* 1 = Modem status changed */
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#define TIMER2_ACTIVE 0x40 /* 1 = Timer 2 output active */
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#define TIMER1_ACTIVE 0x80 /* 1 = Timer 1 output active */
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#define TIMER_ACTIVE 0xC0 /* Either timer active */
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#define SET_8255_MODE 0x98 /* Set up mode for 8255 */
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/***************************************************************************
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* This next section contains the definitions of the various commands *
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* and the parameters that must be passed with the commands and the *
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* results passed back during the result phase. *
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***************************************************************************/
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/***************************************************************************
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* Initialization/Configuration commands and parameters *
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* There are no results for these commands. *
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***************************************************************************/
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#define SET_1_BIT_DELAY_CMD 0xA4 /* cmd to set up one bit delay mode */
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#define RESET_1_BIT_DELAY_CMD 0x64 /* cmd to reset up one bit delay mode */
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#define RESET_1_BIT_DELAY 0x7F /* parameter to reset 1 bit delay */
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#define SET_DATA_XFER_CMD 0x97 /* cmd to set data xfer mode */
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/* NOTE: use this reset command with reset mask to set up for dma adapter */
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#define RESET_DATA_XFER_CMD 0x57 /* cmd to reset data xfer mode */
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#define RESET_TO_USE_DMA 0xFE /* Parameter to set up dma xfer mode */
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#define SET_OPER_MODE_CMD 0x91 /* cmd to set operating mode reg */
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#define SET_FLAG_STREAM 0x01 /* Parameter to set flag stream mode */
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#define SET_PRE_FRAME_MODE 0x02 /* Parameter to set pre_frame sync mode */
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#define SET_BUFFERED_MODE 0x04 /* Parameter to set buffered mode. */
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/* In buffered mode two more result bytes will be sent.. Addr and control */
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/* bytes will follow the RIC, R0 and R1 . */
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#define SET_EARLY_TX_ON 0x08 /* Parameter to set early xmit irpt on */
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#define SET_EOP_IRPT_ON 0x10 /* Parameter to set end of poll irpt on */
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#define SET_HDLC_ABORT 0x20 /* Parameter to set HDLC abort */
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#define SET_NO_DMA 0x01 /* Parameter to set irpt xfer mode */
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#define SET_1_BIT_DELAY 0x80 /* Parameter to set 1 bit delay */
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#define RESET_OPER_MODE_CMD 0x51 /* cmd to reset operating mode reg */
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#define RESET_FLAG_STREAM 0xFE /* Parameter to reset flag stream mode */
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#define RESET_PRE_FRAME_MODE 0xFD /* Parameter to reset pre_frame sync mode *
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#define RESET_BUFFERED_MODE 0xFB /* Parameter to reset buffered mode. */
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#define RESET_EARLY_TX_ON 0xF7 /* Parameter to reset early xmit irpt on */
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#define RESET_EOP_IRPT_ON 0xEF /* Parameter to reset end of poll irpt on *
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#define RESET_HDLC_ABORT 0xDF /* Parameter to reset HDLC abort */
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#define SET_IO_MODE_CMD 0xA0 /* cmd to set serial io mode reg */
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#define RESET_IO_MODE_CMD 0x60 /* cmd to reset serial io mode reg */
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#define RESET_NZRI_DATA 0xFE /* Parameter to reset NZRI encoded data */
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#define RESET_CLOCK_LOOPBACK 0xFD /* Parameter to reset clock loopback */
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#define RESET_DATA_LOOPBACK 0xFB /* Parameter to reset data loopback */
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/***************************************************************************
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* Reset command no parms and no results. The reset is accomplished *
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* outside the normal command interface by writing a 0x01 to the address *
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* WR_TEST_OFFSET then waiting 10 cycles and writing 0x00. *
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***************************************************************************/
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#define START_RESET 0x01 /* start the reset process */
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#define END_RESET 0x00 /* end the reset process */
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/***************************************************************************
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* modem control commands parms and results *
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* 8273 PORT A is read only, PORT B is read/write *
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***************************************************************************/
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#define READ_8273_PORT_A_CMD 0x22 /* Cmd to read from 8273 Port A */
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/* no parms, result in RD_RES_OFFSET */
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#define PORT_A_8273_CTS 0x01 /* 1 = clear to send active */
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#define PORT_A_8273_CD 0x02 /* 1 = carrier detect active */
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#define PORT_A_8273_PA2 0x04 /* 1 = data set ready */
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#define PORT_A_8273_PA3 0x08 /* 1 = CTS changed */
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#define PORT_A_8273_PA4 0x10 /* 1 = DSR changed */
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#define READ_8273_PORT_B_CMD 0x23 /* Cmd to read from 8273 Port B */
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/* no parms, data in RD_RES_OFFSET */
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#define SET_8273_PORT_B_CMD 0xA3 /* Cmd to set 8273 Port B values */
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/* parameter is set_mask, no results */
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#define SET_8273_PORT_B_RTS 0x01 /* mask bit to set req to send bit */
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#define SET_8273_PORT_B_PB1 0x02 /* mask bit to set PB1 bit */
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#define SET_8273_PORT_B_PB2 0x04 /* mask bit to set Data terminal ready */
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#define SET_8273_PORT_B_PB3 0x08 /* mask bit to set PB3 bit */
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#define SET_8273_PORT_B_PB4 0x10 /* mask bit to set V.25 enable bit */
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#define SET_8273_PORT_B_PB5 0x20 /* mask bit to set flag detect bit */
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#define RESET_8273_PORT_B_CMD 0x63 /* Cmd to reset 8273 Port B values */
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/* parameter reset_mask, no results */
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#define RESET_8273_PORT_B_RTS 0xFE /* mask bit to reset req to send bit */
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#define RESET_8273_PORT_B_PB1 0xFD /* mask bit to reset PB1 bit */
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#define RESET_8273_PORT_B_PB2 0xFB /* mask bit to reset Data terminal ready */
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#define RESET_8273_PORT_B_PB3 0xF7 /* mask bit to reset PB3 bit */
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#define RESET_8273_PORT_B_PB4 0xEF /* mask bit to reset V.25 enable bit */
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#define RESET_8273_PORT_B_PB5 0xDF /* mask bit to reset flag detect bit */
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#define MAX_RECV_SIZE 0xFFFF
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#define KMALLOC(dtyp) (dtyp *)xmalloc(sizeof(dtyp), 2, pinned_heap)
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#define KFREE(buf) xmfree((buf), pinned_heap)
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#define OPENP acb->open_struct
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#define DISABLE_INTERRUPTS(lvl) lvl=i_disable(INTCLASS2)
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#define ENABLE_INTERRUPTS(lvl) i_enable(lvl)
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#define SLEEP(el) e_sleep (el, EVENT_SIGRET)
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#define WAKEUP(el) e_wakeup (el)
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#define DDS acb->mpaddp
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#define SLOT (DDS.slot_num)
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#define ARB (DDS.dma_lvl)
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#define MPA_IOCC_ATT (ulong)(IOCC_ATT(DDS.bus_id,IO_IOCC+(SLOT << 16)))
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#define MPA_CHAN_STAT (ulong)(IOCC_ATT(DDS.bus_id,0x004F0060))
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#define MPA_DMA_STAT (ulong)(IOCC_ATT(DDS.bus_id,IO_IOCC+(ARB << 16)+0x60))
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#define MPA_CCR_ATT (ulong)(IOCC_ATT(DDS.bus_id,IO_IOCC+0x2C))
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#define MPA_BUSIO_ATT (ulong)(BUSIO_ATT(DDS.bus_id, DDS.io_addr))
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#define CBSY_0 2
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#define CRBF_1 3
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#define CPBF_0 4
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/***************************************************************************
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* Receive commands parameters and results *
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****************************************************************************/
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#define GEN_RECEIVE_CMD 0xC0 /* cmd to general receive */
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/* parms are LSB then MSB of recv len */
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#define SEL_RECEIVE_CMD 0xC1 /* cmd to selective receive */
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/* parms are LSB then MSB of recv len */
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/* then match addr 1, match addr 2 */
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#define LOOP_RECEIVE_CMD 0xC2 /* cmd to selective loop receive */
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/* parms are LSB then MSB of recv len */
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/* then match addr 1, match addr 2 */
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#define DISABLE_RECV_CMD 0xC5 /* cmd to disable the receiver */
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#define RIC_MASK_LAST_BYTE 0x1F /* used to and with RIC to remove the */
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/* last byte bit count */
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/***************************************************************************
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* Transmit commands parameters and results *
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****************************************************************************/
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#define XMIT_CMD 0xC8 /* cmd to xmit */
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/* parms are LSB then MSB of xmit len */
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/* in buffered mode send A, and C too */
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#define XMIT_ABORT_CMD 0xCC /* cmd to abort xmit */
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/* No parms. */
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#define LOOP_XMIT_CMD 0xCA /* cmd to do loop xmit */
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|
/* parms are LSB then MSB of xmit len */
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|
/* in buffered mode send A, and C too */
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#define LOOP_ABORT_CMD 0xCE /* cmd to abort loop xmit */
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|
/* No parms. */
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|
#define TRANSPARENT_XMIT_CMD 0xC9 /* cmd to do transparent xmit */
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|
/* parms are LSB then MSB of xmit len */
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#define TRANSPARENT_ABORT_CMD 0xCD /* cmd to do transparent xmit */
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|
/* No parms. */
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|
|
|
/***************************************************************************
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* Status reg definitions. Status read from *
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|
* RD_STAT_OFFSET *
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|
***************************************************************************/
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#define TX_RESULT_READY 0x01 /* 1 = Tx result in TxI/R */
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|
#define RX_RESULT_READY 0x02 /* 1 = Rx result in RxI/R */
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|
#define TX_IRPT_ACTIVE 0x04 /* 1 = xmit irpt active */
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|
#define RX_IRPT_ACTIVE 0x08 /* 1 = recv irpt active */
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|
#define CRBF 0x10 /* 1 = command result buffer full */
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|
#define CPBF 0x20 /* 1 = command parm buffer full */
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|
#define CBF 0x40 /* 1 = command buffer full */
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|
#define CBSY 0x80 /* 1 = in command phase */
|
|
#define IRPT_PENDING 0x0C /* to see if there is a TX or RX */
|
|
/* interrupt in the status reg */
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|
|
|
/**************************************************************************
|
|
* MPA MACRO DEFINITIONS *
|
|
**************************************************************************/
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
/* M_INPAGE for checking funky mbufs */
|
|
/* This macro determines if the data portion of an mbuf resides within */
|
|
/* one page -- if TRUE is returned, the data does not cross a page */
|
|
/* boundary. If FALSE is returned, the data does cross a page */
|
|
/* boundary and cannot be d_mastered. */
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
# define M_INPAGE(m) ((((int)MTOD((m), uchar *) \
|
|
& ~(PAGESIZE - 1)) + PAGESIZE) > \
|
|
((int)MTOD((m), uchar *) + (m)->m_len))
|
|
|
|
|
|
/*------------------------------------------------------------------------*/
|
|
/* These BUS accessors are PIO-recovery versions of the original BUS */
|
|
/* accessor macros. The essential difference is that retries are */
|
|
/* performed if pio errors occur; if the retry limit is exceeded, a -1 */
|
|
/* is returned (hence all return an int value). In the cases of */
|
|
/* PIO_GETL and PIO_GETLR, the -1 is indistinguishable from all FF's so */
|
|
/* some heuristic must be used to determine if it is an error (i.e., is */
|
|
/* all FF's a legitimate read value?). */
|
|
/*------------------------------------------------------------------------*/
|
|
|
|
# define C 1 /* Character type of PIO access */
|
|
# define S 2 /* Short type of PIO access */
|
|
# define SR 3 /* Short-reversed type of PIO access */
|
|
# define L 4 /* Long type of PIO access */
|
|
# define LR 5 /* Long-reverse type of PIO access */
|
|
|
|
# define PIO_GETC( p, a ) ((int) PioGet( p, a ))
|
|
|
|
# define PIO_PUTC( p, a, v ) ((int) PioPut( p, a, v ))
|
|
|
|
|
|
/*
|
|
** Macros to get/put caller's parameter block
|
|
** Useful for "arg" in ioctl and for extended paramters on other dd entries.
|
|
** Value is 0 if ok, otherwise EFAULT.
|
|
*/
|
|
#define COPYIN(dvf,usa,dda,siz) \
|
|
( (usa == NULL) ? (EFAULT) : \
|
|
( (dvf & DKERNEL) ? (bcopy(usa,dda,siz), 0) : \
|
|
( copyin(usa,dda,siz) ) ) )
|
|
|
|
#define COPYOUT(dvf,dda,usa,siz) \
|
|
( (usa == NULL) ? (EFAULT) : \
|
|
( (dvf & DKERNEL) ? (bcopy(dda,usa,siz), 0) : \
|
|
( copyout(dda,usa,siz) ) ) )
|