243 lines
5.5 KiB
C
243 lines
5.5 KiB
C
/* @(#)30 1.5.1.21 src/bos/kernel/sys/POWER/overlay.h, sysml, bos412, 9445C412a 10/25/94 11:45:55 */
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#ifndef _H_OVERLAY
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#define _H_OVERLAY
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/*
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* COMPONENT_NAME: (SYSML) Kernel Machine Language
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*
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* FUNCTIONS:
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*
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* ORIGINS: 27, 83
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*
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* (C) COPYRIGHT International Business Machines Corp. 1992, 1994
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* All Rights Reserved
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* Licensed Materials - Property of IBM
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*
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* US Government Users Restricted Rights - Use, duplication or
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* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
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*/
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/*
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* LEVEL 1, 5 Years Bull Confidential Information
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*/
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/* WARNING: Do not change this file without updating ml/POWER/overlay.m4.
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* ml/POWER/sysoverlay.m4 may also need updating.
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*/
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#define MC_FLIH_ADDR 0x0200 /* machine check vector */
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#define MC_FLIH_SIZE 0x0028
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#define DS_FLIH_ADDR 0x0300 /* DSI vector */
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#define DS_FLIH_SIZE 0x000c
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#define IS_FLIH_ADDR 0x0400 /* ISI vector */
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#define IS_FLIH_SIZE 0x000c
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#define AL_FLIH_ADDR 0x0600 /* alignment check handler */
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#define AL_FLIH_SIZE 0x0020
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#define SC_PPC_ADDR 0x0c00 /* Power SC front end */
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#define SC_PPC_SIZE 0x0014
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#define DSE_FLIH_ADDR 0x0a00 /* Direct Store Error */
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#define DSE_FLIH_SIZE 0x0004
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#define TLB_FLIH_IFM_ADDR 0x1000 /* 603 TLB reload handler */
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#define TLB_FLIH_DRM_ADDR 0x1100
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#define TLB_FLIH_DWM_ADDR 0x1200
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#define TLB_FLIH_SIZE 0x0100
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#define CS_PWR_ADDR 0x1020 /* Power CS fast SVC */
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#define CS_PWR_SIZE 0x0020
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#define SC_PWR_ADDR 0x1fe0 /* Power PC SC front end */
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#define SC_PWR_SIZE 0x0004
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/* addresses of millicode routines required by PPC ABI. Do not change
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*/
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#define MULH_ADDR 0x3100
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#define MULH_SIZE 0x0080
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#define MULL_ADDR 0x3180
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#define MULL_SIZE 0x0080
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#define DIVSS_ADDR 0x3200
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#define DIVSS_SIZE 0x0080
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#define DIVUS_ADDR 0x3280
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#define DIVUS_SIZE 0x0080
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#define QUOSS_ADDR 0x3300
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#define QUOSS_SIZE 0x0080
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#define QUOUS_ADDR 0x3380
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#define QUOUS_SIZE 0x0080
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/*
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* addresses of atomic lock primitives required by PPC ABI.
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* Do not change.
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*/
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#define _CLEAR_LOCK_ADDR 0x3400
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#define _CLEAR_LOCK_SIZE 0x0020
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#define _CHECK_LOCK_ADDR 0x3420
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#define _CHECK_LOCK_SIZE 0x0040
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/* Overlay of machine dependent cs() function
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*/
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#define CS_ADDR 0x3460
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#define CS_SIZE 0x0040
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/*
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* area reserved for future use. will have user read access.
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*/
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#define NONPRIV_RESERV_ADDR 0x8000
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#define NONPRIV_RESERV_SIZE PSIZE
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/*
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* i_enable/i_disable are aligned to a 256 byte boundry for better
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* cache affinity
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*/
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/* i_disable/disable_lock go together now--do not modify one without the other! */
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#define I_DISABLE_ADDR 0x9000
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#define I_DISABLE_SIZE 0x0004
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#define DISABLE_LOCK_ADDR 0x9004
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#define DISABLE_LOCK_SIZE 0x02FC
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/* i_enable/unlock_enable go together now--do not modify one without the other! */
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#define I_ENABLE_ADDR 0x9300
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#define I_ENABLE_SIZE 0x0004
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#define UNLOCK_ENABLE_ADDR 0x9304
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#define UNLOCK_ENABLE_SIZE 0x01FC
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#define SIMPLE_LOCK_ADDR 0x9500
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#define SIMPLE_LOCK_SIZE 0x0400
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#define SIMPLE_UNLOCK_ADDR 0x9900
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#define SIMPLE_UNLOCK_SIZE 0x0200
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#define FETCH_AND_ADD_ADDR 0x9B00
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#define FETCH_AND_ADD_SIZE 0x0060
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/* The following are overlay addresses for routines that can be called
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* directly from base device drivers. Do not change the address of these
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* functions. If it becomes a requirement to change the address wait for
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* a major release. Changing these address breaks binary compatibility with
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* device drivers.
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*/
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#define BUSGETC_ADDR 0xA000
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#define BUSGETC_SIZE 0X0060
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#define BUSGETS_ADDR 0xA060
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#define BUSGETS_SIZE 0x0060
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#define BUSGETSR_ADDR 0xA0c0
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#define BUSGETSR_SIZE 0x0060
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#define BUSGETL_ADDR 0xA120
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#define BUSGETL_SIZE 0x0060
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#define BUSGETLR_ADDR 0xA180
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#define BUSGETLR_SIZE 0x0060
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#define BUSPUTC_ADDR 0xA1e0
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#define BUSPUTC_SIZE 0x0060
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#define BUSPUTS_ADDR 0xA240
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#define BUSPUTS_SIZE 0x0060
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#define BUSPUTL_ADDR 0xA2a0
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#define BUSPUTL_SIZE 0x0060
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#define BUSPUTSR_ADDR 0xA300
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#define BUSPUTSR_SIZE 0x0060
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#define BUSPUTLR_ADDR 0xA360
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#define BUSPUTLR_SIZE 0x0060
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#define BUSCPY_ADDR 0xA3c0
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#define BUSCPY_SIZE 0x00a0
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/*
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* Keep all read/write segment registers in the same cache
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* line (64 bytes). These sizes are exact. Do not change
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* these address without updating inline.h
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*/
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#define CHGSR_ADDR 0xA480
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#define CHGSR_SIZE 0x0018
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#define MTSR_ADDR 0xA498
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#define MTSR_SIZE 0x0014
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#define MFSR_ADDR 0xA4AC
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#define MFSR_SIZE 0x000c
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#define MFSRI_ADDR 0xA4B8
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#define MFSRI_SIZE 0x0008
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#define COMPARE_AND_SWAP_ADDR 0xA4C0
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#define COMPARE_AND_SWAP_SIZE 0x0100
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#define TEST_AND_SET_ADDR 0xA5C0
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#define TEST_AND_SET_SIZE 0x0100
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#define SIMPLE_LOCK_TRY_ADDR 0xA6C0
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#define SIMPLE_LOCK_TRY_SIZE 0x0200
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#define RSIMPLE_LOCK_ADDR 0xA8C0
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#define RSIMPLE_LOCK_SIZE 0x0180
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#define RSIMPLE_LOCK_TRY_ADDR 0xAA40
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#define RSIMPLE_LOCK_TRY_SIZE 0x0180
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#define RSIMPLE_UNLOCK_ADDR 0xABC0
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#define RSIMPLE_UNLOCK_SIZE 0x0100
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#define LOCKL_ADDR 0xACC0
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#define LOCKL_SIZE 0x0200
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#define FETCH_AND_OR_ADDR 0xAEC0
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#define FETCH_AND_OR_SIZE 0x0060
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#define FETCH_AND_NOP_ADDR 0xAF20
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#define FETCH_AND_NOP_SIZE 0x0060
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#define FETCH_AND_AND_ADDR 0xAF80
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#define FETCH_AND_AND_SIZE 0x0060
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#define FETCH_AND_ADD_H_ADDR 0xB000
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#define FETCH_AND_ADD_H_SIZE 0x0100
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#define UNLOCKL_ADDR 0xB100
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#define UNLOCKL_SIZE 0x0200
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#ifdef _POWER_MP
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/* ppda/csa/curthread management
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*/
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#define MY_PPDA_ADDR 0xb400
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#define MY_PPDA_SIZE 0x0008
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#define MY_CSA_ADDR 0xb408
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#define MY_CSA_SIZE 0x0020
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#define GET_CURTHREAD_ADDR 0xb428
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#define GET_CURTHREAD_SIZE 0x0020
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#define SET_CSA_ADDR 0xb448
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#define SET_CSA_SIZE 0x0018
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#define SET_CURTHREAD_ADDR 0xb460
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#define SET_CURTHREAD_SIZE 0x0010
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#endif
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#endif /* _H_OVERLAY */
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