196 lines
4.8 KiB
C
196 lines
4.8 KiB
C
/* @(#)57 1.12.1.8 src/bos/kernel/sys/POWER/reg.h, sysproc, bos411, 9434B411a 8/22/94 16:51:58 */
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/*
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* COMPONENT_NAME: SYSPROC
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*
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* FUNCTIONS: FPR_loc
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* GPR_loc
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* ISWALIGN
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* ISWRITEREG
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* SPR_loc
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* SPR_size
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* VALID_ADDR
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* VALID_FPR
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* VALID_GPR
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* VALID_SPR
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*
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* ORIGINS: 3, 27, 83
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*
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*
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* (C) COPYRIGHT International Business Machines Corp. 1988, 1994
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* All Rights Reserved
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* Licensed Materials - Property of IBM
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* US Government Users Restricted Rights - Use, duplication or
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* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
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*/
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/*
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* LEVEL 1, 5 Years Bull Confidential Information
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*/
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#ifndef _H_REG
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#define _H_REG
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/* macro defines for general purpose registers, all 32-bit, sequential no's */
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#define GPR0 0
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#define GPR1 1
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#define GPR2 2
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#define GPR3 3
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#define GPR4 4
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#define GPR5 5
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#define GPR6 6
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#define GPR7 7
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#define GPR8 8
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#define GPR9 9
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#define GPR10 10
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#define GPR11 11
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#define GPR12 12
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#define GPR13 13
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#define GPR14 14
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#define GPR15 15
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#define GPR16 16
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#define GPR17 17
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#define GPR18 18
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#define GPR19 19
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#define GPR20 20
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#define GPR21 21
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#define GPR22 22
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#define GPR23 23
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#define GPR24 24
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#define GPR25 25
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#define GPR26 26
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#define GPR27 27
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#define GPR28 28
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#define GPR29 29
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#define GPR30 30
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#define GPR31 31
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/* miscellaneous special purpose registers - 32-bit, sequential no's */
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#define IAR 128 /* instruction address register */
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#define MSR 129 /* machine state register */
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#define CR 130 /* condition register */
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#define LR 131 /* link register */
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#define CTR 132 /* count register */
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#define XER 133 /* fixed point exception */
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#define MQ 134 /* multiply/quotient register */
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#define TID 135 /* tid register */
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#define FPSCR 136 /* floating point status reg */
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#define FPINFO 138 /* floating point info reg */
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#define FPSCRX 148 /* floating point sreg ext. */
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/* macro defines for floating point registers - 64-bit, sequential no's */
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#define FPR0 256
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#define FPR1 257
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#define FPR2 258
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#define FPR3 259
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#define FPR4 260
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#define FPR5 261
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#define FPR6 262
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#define FPR7 263
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#define FPR8 264
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#define FPR9 265
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#define FPR10 266
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#define FPR11 267
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#define FPR12 268
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#define FPR13 269
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#define FPR14 270
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#define FPR15 271
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#define FPR16 272
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#define FPR17 273
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#define FPR18 274
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#define FPR19 275
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#define FPR20 276
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#define FPR21 277
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#define FPR22 278
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#define FPR23 279
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#define FPR24 280
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#define FPR25 281
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#define FPR26 282
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#define FPR27 283
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#define FPR28 284
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#define FPR29 285
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#define FPR30 286
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#define FPR31 287
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/* miscellaneous mapping for software conventions */
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#define STKP GPR1
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#define PCP GPR1
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#define TOC GPR2
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#define ARG1 GPR3
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#define ARG2 GPR4
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#define ARG3 GPR5
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#define ARG4 GPR6
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/* calling convention values */
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#define STACK_FLOOR 256
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#ifdef _KERNEL
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/*
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* NAME: Macro definitions for machine dependent ptrace values
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*/
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/* macros to validate register values, returns 1 or 0 */
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#define VALID_GPR(x) ((x) >= GPR0 && (x) <= GPR31)
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#define VALID_SPR(x) ((x) >= IAR && (x) <= FPSCR)
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#define VALID_FPR(x) ((x) >= FPR0 && (x) <= FPR31)
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/* macros to convert passed register to actual register address */
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#define GPR_loc(mp, x) \
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(char *)(&(mp->gpr[(int)(x) - GPR0]))
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#define SPR_loc(mp, x) \
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(char *)(&(mp->iar) + (int)(x) - IAR)
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#define FPR_loc(mp, x) \
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(char *)(&(mp->fpr[(int)(x) - FPR0]))
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/* macros to provide data transfer sizes */
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#define GPR_size (sizeof(uthr0.ut_save.gpr[0]))
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#define SPR_size(x) (sizeof(uthr0.ut_save.iar))
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#define FPR_size (sizeof(uthr0.ut_save.fpr[0]))
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/* is this word aligned */
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#define ISWALIGN(x) ((int)(x) & (sizeof(int) - 1) ? 0 : 1)
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/* is this a valid area for a debugger to be accessing */
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#define VALID_ADDR(x) \
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(( (((int)(x) >> SEGSHIFT) == PRIVSEG && SEGOFFSET(x) >= U_REGION_SIZE)\
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|| ((int)(x) >> SEGSHIFT) == KERNEXSEG ) ? 0 : 1 )
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#define ISWRITEREG(x) \
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(VALID_GPR(((x)-(int *)&((struct mstsave *)0)->gpr[0])) || \
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VALID_SPR(((x)-(int *)&((struct mstsave *)0)->iar)) )
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#endif /* _KERNEL */
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#ifdef _KERNSYS
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/*
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* Construct problem-program MSR, allowing the user to specify certain
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* bits.
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*
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* MSR bit forced to Signal handler can specify
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* ------- --------- --------------------------
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* EE 1 AL
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* FP 0
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* FE 0
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* IE 0
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* ME 1
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* IP 0
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* IR 1
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* DR 1
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* PR 1 for user thread
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*/
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#define SANITIZE_MSR(x) (x) = (MSR_EE | MSR_ME | MSR_IR | MSR_DR | MSR_PR) | \
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((x) & (MSR_AL))
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#define MASK_FP(x) \
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((char)(((x) >> FP_SYNC_IMP_S) & (FP_IMP_INT | FP_SYNC_TASK)))
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#define UPDATE_FPINFO(x) \
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(__power_pc() ? \
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MASK_FP(x) : \
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MASK_FP(x) & FP_SYNC_TASK ? \
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FP_SYNC_TASK : \
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(char)( ( MASK_FP(x) & FP_IMP_INT ) && \
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( __power_rs2()) ))
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#endif /* _KERNSYS */
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#endif /* _H_REG */
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