692 lines
28 KiB
C
692 lines
28 KiB
C
/* @(#)50 1.7.1.3 src/bos/kernel/sys/POWER/rosinfo.h, rosipl, bos41J, 9514A_all 3/28/95 22:43:44 */
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#ifndef _H_ROSINFO
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#define _H_ROSINFO
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/*
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* COMPONENT_NAME: (ROSIPL) ros code header file rosinfo.h
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*
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* ORIGINS: 27
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*
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* (C) COPYRIGHT International Business Machines Corp. 1988, 1995
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* All Rights Reserved
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* Licensed Materials - Property of IBM
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*
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* US Government Users Restricted Rights - Use, duplication or
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* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
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*/
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#ifdef _POWER
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typedef struct ros_entry_table { /* invalid address = -1 */
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unsigned int *warm_ipl; /* software reipl 01*/
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unsigned int *reserved_2; /* reserved 02*/
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unsigned int *detmedia; /* NIO diskette restore 03*/
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unsigned int *detdata; /* NIO diskette read 04*/
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unsigned int *detdrive; /* SCSI disk restore 05*/
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unsigned int *scsidata; /* SCSI disk read 06*/
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unsigned int *sla_restore; /* SLA restore 07*/
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unsigned int *sla_read; /* SLA read 08*/
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unsigned int *crc; /* Cylic Redundency Check 09*/
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unsigned int *manfacturing_led_syncaddr; /* fixed address for mfg use10*/
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unsigned int *AT_BIOS_compressed; /* PC AT BIOS code, 11*/
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unsigned int *reserved_05; /* reserved 12*/
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unsigned int *reserved_04; /* reserved 13*/
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unsigned int *reserved_03; /* reserved 14*/
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unsigned int *reserved_02; /* reserved 15*/
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unsigned int *reserved_01; /* reserved 16*/
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unsigned int *reserved_00; /* reserved 17*/
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/* the offset to the start of compressed ros in the actual compressed */
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/* ROS image. this will be the starting location to be uncompressed and */
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/* loaded into RAM space */
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unsigned int *start_of_cros;
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/* the offset to the end of compressed ros in the actual compressed */
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/* ROS image. this location does not get uncompressed */
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unsigned int *end_of_cros;
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/* the offset to the start of the uncompressed ros code */
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unsigned int *start_of_ucros;
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/* the offset to the end of the uncompressed ros code */
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unsigned int *end_of_ucros;
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/* the offset to the start of the ros code */
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unsigned int *start_of_ros;
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/* the offset to the end of the ros code */
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unsigned int *end_of_ros;
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/* the offset to the start of the token ring ucode1 */
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unsigned int *tok_start1;
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/* the offset to the end of the token ring ucode1 */
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unsigned int *tok_end1;
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/* the offset to the start of the token ring ucode2 */
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unsigned int *tok_start2;
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/* the offset to the end of the token ring ucode2 */
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unsigned int *tok_end2;
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/* the offset to the start of the lega ucode */
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unsigned int *lega_start;
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/* the offset to the end of the lega ucode */
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unsigned int *lega_end;
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/* the offset to the start of the scsi script */
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unsigned int *scsi_start;
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/* the offset to the end of the scsi script */
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unsigned int *scsi_end;
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/* the offset to the start of the font bitmap */
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unsigned int *font_start;
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/* the offset to the end of the font bitmap */
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unsigned int *font_end;
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/* the offset to the start of the format control ascii */
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unsigned int *fc_start;
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/* the offset to the end of the format control ascii */
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unsigned int *fc_end;
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/* the offset to the start of the text ascii */
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unsigned int *UStext_start;
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/* the offset to the end of the text ascii */
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unsigned int *UStext_end;
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/* the offset to the start of the text ascii */
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unsigned int *FRtext_start;
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/* the offset to the end of the text ascii */
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unsigned int *FRtext_end;
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/* the offset to the start of the text ascii */
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unsigned int *GRtext_start;
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/* the offset to the end of the text ascii */
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unsigned int *GRtext_end;
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/* the offset to the start of the text ascii */
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unsigned int *SVtext_start;
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/* the offset to the end of the text ascii */
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unsigned int *SVtext_end;
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/* the offset to the start of the text ascii */
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unsigned int *ITtext_start;
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/* the offset to the end of the text ascii */
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unsigned int *ITtext_end;
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/* the offset to the start of the text ascii */
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unsigned int *BEtext_start;
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/* the offset to the end of the text ascii */
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unsigned int *BEtext_end;
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/* the offset to the start of the text ascii */
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unsigned int *NOtext_start;
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/* the offset to the end of the text ascii */
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unsigned int *NOtext_end;
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/* the offset to the start of the text ascii */
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unsigned int *SPtext_start;
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/* the offset to the end of the text ascii */
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unsigned int *SPtext_end;
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/* the offset to the start of the "buffer zone" */
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unsigned int *buff_start;
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/* the offset to the end of the "buffer zone" */
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unsigned int *buff_end;
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/* the offset to the start of the compressed AT BIOS code */
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unsigned int *bios_start;
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/* the offset to the end of the compressed AT BIOS code */
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unsigned int *bios_end;
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/* the length of the first compressed ros field */
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unsigned int *c1_length;
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/* the offset to the start of the font bitmap */
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unsigned int *font_start640;
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/* the offset to the end of the font bitmap */
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unsigned int *font_end640;
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} ROS_ENTRY_TABLE, *ROS_ENTRY_TABLE_PTR;
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typedef struct simm_definition {
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unsigned char SIMM_7and8; /* One SIMM is a nibble wide (four bits) */
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unsigned char SIMM_3and4; /* and will have the value of 0x0(good) or */
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unsigned char SIMM_5and6; /* 0xf(bad). */
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unsigned char SIMM_1and2;
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} SIMM_DEFINITION;
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typedef struct ipl_info {
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/* The following two entries are reserved for IPL ROM usage.
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* Pointer to the IPL Controller and Device Interface Routine in Memory. The
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* size is Memory allocated for the IPL Controller and Device Interface Routine
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* NOTE: validity of this pointer is not guaranteed to be correct after
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* IPL ROM has given control to the loaded code.
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*/
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unsigned int *iplc_and_dir_ptr;
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unsigned int iplc_and_dir_size;
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/* The following two entries are reserved for IPL ROM usage.
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* Pointer to the NVRAM expansion code in Memory.
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* The size is Memory allocated for the NVRAM expansion code.
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* NOTE: validity of this pointer is not guaranteed to be correct after
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* IPL ROM has given control to the loaded code.
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*/
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unsigned int *ram_exp_code_ptr;
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unsigned int ram_exp_code_size;
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/* The following two entries are reserved for IPL ROM usage.
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* Initial pointer to the IPL ROM Stack's high address in Memory.
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* The size is Memory allocated for the IPL ROM Stack.
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* NOTE: validity of this pointer is not guaranteed to be correct after
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* IPL ROM has given control to the loaded code.
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*/
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unsigned int *ipl_ros_stack_ptr;
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unsigned int ipl_ros_stack_size;
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/* The following two entries are reserved for IPL ROM usage.
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* Pointer to the IPL Record in Memory.
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* The size is Memory allocated for the IPL Record area.
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* NOTE: validity of this pointer is not guaranteed to be correct after
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* IPL ROM has given control to the loaded code.
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*/
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unsigned int *ipl_rec_ptr;
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unsigned int ipl_rec_size;
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/* The following entry is reserved for IPL ROM usage.
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* Pointer to the lowest address needed by IPL ROM in Memory.
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* NOTE: validity of this pointer is not guaranteed to be correct after
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* IPL ROM has given control to the loaded code.
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*/
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unsigned int *ros_workarea_low_boundry;
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/* The following two entries are reserved for IPL ROM usage.
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* Pointer to the IPL ROM entry table.
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* The size in ROM for the entry table.
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* NOTE: In order to address IPL ROM, translate mode must be off and
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* Segment Register 15 set.
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*/
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unsigned int *ros_entry_table_ptr;
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unsigned int ros_entry_table_size;
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/* The following entry is reserved for IPL ROM usage.
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* The memory bit map's number of bytes per bit.
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* NOTE: the default size is 16K/bit
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*/
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unsigned int bit_map_bytes_per_bit;
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/* The following entry is reserved for IPL ROM usage.
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* The highest addressable real memory address byte+1
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* Note: All real memory addresses below this value are in range, addressing
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* memory at this address or above will cause an address out of range
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* exception. The appropriate Segment Register T-bit must be set to zero
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* in order to address memory.
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*/
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unsigned int ram_size;
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/*
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* The model field contains information which allows software to determine
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* hardware type, data cache size, and instruction cache size.
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*
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* The model field is decoded as follows:
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* 0xWWXXYYZZ
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*
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* case 1: WW = 0x00 This means that the hardware is SGR ss32 or SGR ss64
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* (ss is speed in MH). The instruction cache is 8K bytes.
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* XX = reserved
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* YY = reserved
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* ZZ = the model code:
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* bits 0 & 1 (low order bits) - indicate style type
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* 00 = Tower 01 = Desktop
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* 10 = Rack 11 = Reserved
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* bits 2 & 3 - indicate relative speed of processor
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* 00 = Low 01 = Medium
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* 10 = High 11 = Very high
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* bit 4 - Indicates number of combo chips.
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* 0 = 2 combo chips
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* 1 = 1 combo chip
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* bit 5 - Indicates the number of DCU's.
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* 0 = 4 DCU's, data cache is 64 K bytes
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* 1 = 2 DCU's, data cache is 32 K bytes
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* bits 6 & 7 (high order bits) - Reserved.
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*
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* case 2: WW is nonzero.
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* WW = 0x01 This means that the hardware is SGR ss32 or SGR ss64
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* (ss is speed in MH) - RS1
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* WW = 0x02 means the hardware is RSC.
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* WW = 0x04 means the hardware is RS2 ( POWER2).
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* WW = 0x08 means the hardware is PowerPC.
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* XX has the following bit definitions:
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* bits 0 & 1 (low order bits) - indicate package type
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* 00 = Tower 01 = Desktop
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* 10 = Rack 11 = Entry Server Type
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* bit 2 - AIX Hardware Verification Test Supported (rspc)
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* bit 3 - AIX Hardware Error Log Analysis Supported (rspc)
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* bits 4 through 7 are reserved.
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* YY = reserved.
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* ZZ = the model code. No further information can be obtained
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* from this byte.
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*
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* The instruction cache K byte size is obtained from entry icache.
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* The data cache K byte size is obtained from entry dcache.
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*
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*/
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unsigned int model;
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/* The following entry is reserved for IPL ROM usage.
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* Power Status and keylock Register Decode. IO Address 0x04000E4
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* This is a 32 bit register:
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* Power Status bits 0 to 9.
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* reserved bits 10 to 27.
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* keylock decode bits 28 to 31 are as follows:
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* 28 29 30 31
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* 1 1 X X Workstation
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* 0 1 X X Supermini
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* 0 0 X X Expansion
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* X X 1 1 Normal keylock position
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* X X 1 0 Service keylock position
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* X X 0 1 Secure keylock position
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* X is don't care
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*/
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unsigned int Power_Status_and_keylock_reg;
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/*
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* This value is initially set to zero during power-on IPL and is incremented
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* by one with each invocation of ROM warm IPL.
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*/
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int soft_ipl_flag;
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/* The following entries are reserved for IPL ROM usage.
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* The following entries are set and used by the IPL Controller.
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*/
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int nvram_section_1_valid; /* 0 if CRC miscompare */
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int nvram_exp_code_valid; /* 0 if CRC miscompare */
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unsigned char previpl_device[36]; /* last normal mode ipl device*/
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char reserved[28]; /* reserved for last ipl needs*/
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/* The following entries are reserved for IPL ROM usage.
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* Pointer to the IPL Control Block in Memory.
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* During warm IPL if it is necessary this pointer will be used to reestablish
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* the original location of the IPL Control Block in memory to avoid any
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* collision with the code that is about to be loaded by the IPL process.
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*/
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unsigned int *iplcb_ptr; /* IPL Control Block pointer */
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/* The following entries are reserved for IPL ROM usage.
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* Pointer to compressed BIOS code in the IPL ROM.
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* The size of BIOS code in bytes in the IPL ROM.
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* NOTE: In order to address IPL ROM, translate mode must be off and
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* Segment Register 15 set.
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*/
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unsigned char *BIOS_code_ptr;
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unsigned int BIOS_code_size;
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/* The following entriy is reserved for IPL ROM usage.
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* Pointer to the RAM copy of the Core Sequence Controller.
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* Saved by IPLCBinit after moving the ROM to RAM.
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*/
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unsigned int *CSC_in_RAM_ptr;
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/*
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* Storage Configuration Registers.
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* This is the value the IPL ROM assigned during the power up phase of IPL.
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* There are 16 elements, one for each of the extents.
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* NOTE: see the IPL Control Block entry extent_errinfo for any error
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* information that was saved when the cre was set.
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*/
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unsigned int cre[16];
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/*
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* Bit Steering Registers.
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* This is the value the IPL ROM assigned during the power up phase of IPL.
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* There are 16 elements, one for each of the extents.
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* NOTE: see the IPL Control Block entry memcd_errinfo for any SIMM error
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* information that was saved when the bscr was set.
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*/
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unsigned int bscr[16];
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/* The following entries are reserved for IPL ROM usage.
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* NOTE: These fields are not currently implemented and there is no future
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* plans to implement them.
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*/
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struct {
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unsigned int syndrome;
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unsigned int address;
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unsigned int status;
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} single_bit_error[16];
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unsigned int reserved_array[5*16];
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/* Memory extent test indicator.
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* Marked tested after each memory extent is tested during the ROM IPL.
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* There are 16 elements, one for each of the extents.
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*/
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unsigned char extent_tested_ind[16]; /* 0 = untested, 1 = tested */
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/* Memory bit steering register setting conflict indicator.
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* Marked after each memory extent is tested during the ROM IPL.
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* There are 16 elements, one for each of the extents.
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* Note: the bscr associated with the tested memory extent is compared to the
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* bscr data in the Non Volatile RAM(NVRAM). If there is a miscompare
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* then the conflict indicator is set.
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*/
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unsigned char bit_steer_conflict[16]; /* 1 = Bit Steering conflict */
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/* The following entries are reserved for IPL ROM usage.
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* The following entries are set by the IPL Controller.
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*/
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unsigned int ipl_dev_ledval; /* led value at ipl time */
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unsigned int ipl_dev_driveval; /*ipl device drive# (non scsi)*/
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char unused[18]; /* */
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/*
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* The following entries are copied from the IPL ROM Vital Product Data area.
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* These values are used to determine the machine hardware level.
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*/
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char vpd_planar_part_number[8];
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char vpd_planar_ec_number[8];
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char vpd_processor_serial_number[8];
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char vpd_ipl_ros_part_number[8];
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char vpd_ipl_ros_ver_lev_id[14];
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char ipl_ros_copyright[49];
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char ipl_ros_timestamp[10];
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/*
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* The following entries are copied from data in the Non Volatile RAM(NVRAM).
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* These values are used to determine the machine hardware level.
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*/
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union {
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unsigned int chip_signature;
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struct CHIP_SIGNATURE {
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unsigned char cop_bus_address;
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unsigned char obsolete_u_num;
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unsigned char dd_number;
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unsigned char part_number;
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} CHIP_SIGNATURE;
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} floating_point, fixed_point, instruction_cache_unit, storage_control_unit,
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combo_1, combo_2, data_control_unit_0, data_control_unit_1,
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data_control_unit_2, data_control_unit_3;
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/*
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* Memory card SIMM error information. SIMM is a replaceable memory card part.
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* There are 8 possible cards(slot A to H) with 8 SIMMs(1 to 8) per card.
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* There are two cache line sizes(see the IPL Control Block entry
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* cache_line_size). If the size is 128 then use the memory_card_1n data to
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* find which SIMM(s) are bad. Otherwise use the memory_card_9n or
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* memory_card_Tn data. See the IPL Control Block entry IO_planar_level_reg
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* to determine if there is a table top system present.
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* The n after the 1 or 9 or T represents the slot number(A thru H).
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*/
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union {
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char memcd_errinfo[32]; /* holds err info for memory cards */
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unsigned int slots_of_SIMMs[8]; /* When 0x0 then no SIMM was marked bad*/
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struct {
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struct simm_definition /* Cache line size of 128 */
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memory_card_1H, memory_card_1F, memory_card_1G, memory_card_1E,
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memory_card_1D, memory_card_1B, memory_card_1C, memory_card_1A;
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} STUFF_1;
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struct {
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struct simm_definition /* Cache line size of 64 */
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memory_card_9H, memory_card_9D, memory_card_9F, memory_card_9B,
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memory_card_9G, memory_card_9C, memory_card_9E, memory_card_9A;
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} STUFF_9;
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struct {
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struct simm_definition /* Cache line size of 64 */
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memory_card_TB, memory_card_TC;
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} STUFF_T;
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} SIMM_INFO;
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/*
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* MESR error information at IPL ROM memory configuration time.
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* There are two cache line sizes(see the IPL Control Block entry
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* cache_line_size). If the size is 128 then use the ext_n_slot_XandY data to
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* find the extent MESR. Otherwise use the ext_n_slot_X data.
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* The _n_ is the extent number while _X andY are the slots associated with the
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* extent.
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* NOTE: find one of the following values in the word variable,
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* 0x00000000 no MESR error occurred when configuring this extent.
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* 0xe0400000 a timeout error occurred while trying to configuring this
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* extent. No memory card is in the slot for this extent.
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* OTHERWISE an error occurred which means the memory card is present but
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* not being used.
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*/
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union {
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char extent_errinfo[64]; /* holds mesr contents (error info) */
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struct { /* Cache line size of 128 */
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unsigned int
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ext_0_slot_HandD, ext_1_slot_HandD, ext_2_slot_HandD, ext_3_slot_HandD,
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ext_4_slot_FandB, ext_5_slot_FandB, ext_6_slot_FandB, ext_7_slot_FandB,
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ext_8_slot_GandC, ext_9_slot_GandC, ext_10_slot_GandC,ext_11_slot_GandC,
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ext_12_slot_EandA,ext_13_slot_EandA,ext_14_slot_EandA,ext_15_slot_EandA;
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} MESR_err_1;
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struct { /* Cache line size of 64 */
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unsigned int
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ext_0_slot_H, ext_1_slot_H, ext_2_slot_D, ext_3_slot_D,
|
|
ext_4_slot_F, ext_5_slot_F, ext_6_slot_B, ext_7_slot_B,
|
|
ext_8_slot_G, ext_9_slot_G, ext_10_slot_C, ext_11_slot_C,
|
|
ext_12_slot_E, ext_13_slot_E, ext_14_slot_A, ext_15_slot_A;
|
|
} MESR_err_9;
|
|
} CONFIG_ERR_INFO;
|
|
|
|
char unused_errinfo[64]; /* reserved for future use */
|
|
|
|
/*
|
|
* Memory card VPD data area
|
|
* There are two cache line sizes(see the IPL Control Block entry
|
|
* cache_line_size). If the size is 128 then use the ext_n_slot_XandY data to
|
|
* find the extent VPD. Otherwise use the ext_n_slot_X data.
|
|
* The _n_ is the extent number while _X andY are the slots associated with the
|
|
* extent.
|
|
* NOTE: find one of the following values in the word variable,
|
|
* 0xFFFFFFFF memory card is present but did not respond with VPD info.
|
|
* 0x22222222 memory card is present but gave error responses.
|
|
* 0x11111111 No memory card is in the slot for this extent.
|
|
* OTHERWISE this must be good VPD.
|
|
*/
|
|
union {
|
|
char memcd_vpd[128];
|
|
struct { /* Cache line size of 128 */
|
|
char
|
|
ext_0_slot_HandD[20],
|
|
ext_4_slot_FandB[20],
|
|
ext_8_slot_GandC[20],
|
|
ext_12_slot_EandA[20] ;
|
|
} memory_VPD_1;
|
|
struct { /* Cache line size of 64 */
|
|
char
|
|
ext_0_slot_H[10], dmy_0[2],
|
|
ext_2_slot_D[10], dmy_2[2],
|
|
ext_4_slot_F[10], dmy_4[2],
|
|
ext_6_slot_B[10], dmy_6[2],
|
|
ext_8_slot_G[10], dmy_8[2],
|
|
ext_10_slot_C[10], dmy_10[2],
|
|
ext_12_slot_E[10], dmy_12[2],
|
|
ext_14_slot_A[10], dmy_14[2];
|
|
} memory_VPD_9;
|
|
} MEMCD_VPD;
|
|
|
|
/* Cache Line size
|
|
* Double card cache line size is 128 bytes, while single card cache line size
|
|
* is 64 bytes.
|
|
*/
|
|
int cache_line_size;
|
|
|
|
/*
|
|
* Component Reset Register test results. For BUID 20
|
|
* There are four data tests 0x00, 0xAA, 0x55 and 0xFF, when all tests are
|
|
* successful then the value found here will be 0x00AA55FF. Any other value
|
|
* indicates stuck bits in the component reset register(stuck on or stuck off).
|
|
*/
|
|
int CRR_results;
|
|
|
|
|
|
/* IO Planar Level Register
|
|
* Use this value to determine if this is a family 2 or table top system.
|
|
* 0x1YYXXXXX is a family 2.
|
|
* 0x8YYXXXXX is a table/desk top.
|
|
* YY defines the Engineering Level. X is reserved.
|
|
*
|
|
* An IO Planar value of -1 indicates NOT present.
|
|
*
|
|
* The value in the most significant byte has the following meaning:
|
|
* 0x80 table/desk top.
|
|
* 0x40 reserved
|
|
* 0x20 reserved
|
|
* 0x10 Rack Planar
|
|
* 0x08 Standard IO
|
|
* 0x04 Power connector NOT connected
|
|
* 0x02 reserved
|
|
* 0x01 reserved
|
|
*
|
|
*/
|
|
int IO_planar_level_reg; /* base IO planar on BUID 20 */
|
|
int IO_planar_level_reg_21; /* IO planar on BUID 21 */
|
|
int IO_planar_level_reg_22; /* IO planar on BUID 22 */
|
|
int IO_planar_level_reg_23; /* IO planar on BUID 23 */
|
|
|
|
/*
|
|
* Component Reset Register test results. For (OPTIONAL feature) BUID 21
|
|
* There are four data tests 0x00, 0xAA, 0x55 and 0xFF, when all tests are
|
|
* successful then the value found here will be 0x00AA55FF. Any other value
|
|
* indicates stuck bits in the component reset register(stuck on or stuck off).
|
|
* If the value is 0xffffffff then most likely the IO planar is not connected.
|
|
*/
|
|
int CRR_results_21;
|
|
|
|
/*
|
|
* Component Reset Register test results. For (future OPTIONAL feature) BUID 22
|
|
* There are four data tests 0x00, 0xAA, 0x55 and 0xFF, when all tests are
|
|
* successful then the value found here will be 0x00AA55FF. Any other value
|
|
* indicates stuck bits in the component reset register(stuck on or stuck off).
|
|
* If the value is 0xffffffff then most likely the IO planar is not connected.
|
|
*/
|
|
int CRR_results_22;
|
|
|
|
/*
|
|
* Component Reset Register test results. For (future OPTIONAL feature) BUID 23
|
|
* There are four data tests 0x00, 0xAA, 0x55 and 0xFF, when all tests are
|
|
* successful then the value found here will be 0x00AA55FF. Any other value
|
|
* indicates stuck bits in the component reset register(stuck on or stuck off).
|
|
* If the value is 0xffffffff then most likely the IO planar is not connected.
|
|
*/
|
|
int CRR_results_23;
|
|
|
|
/*
|
|
* Component Reset Register test results. For (BASE feature) BUID 20
|
|
* There are four data tests 0x0s, 0xAs, 0x5s and 0xFs, when all tests are
|
|
* successful then the value found here will be <see below> Any other value
|
|
* indicates stuck bits in the component reset register(stuck on or stuck off).
|
|
* If the value is 0xffffffff in CRR_results_20_0, then most likely the
|
|
* IO planar is not connected.
|
|
*/
|
|
int CRR_results_20_0; /* should contain 0x00000000 */
|
|
int CRR_results_20_a; /* should contain 0xaaaaaaaa */
|
|
int CRR_results_20_5; /* should contain 0x55555555 */
|
|
int CRR_results_20_f; /* should contain 0xffffffff */
|
|
|
|
/*
|
|
* Component Reset Register test results. For (OPTIONAL feature) BUID 21
|
|
* There are four data tests 0x0s, 0xAs, 0x5s and 0xFs, when all tests are
|
|
* successful then the value found here will be <see below> Any other value
|
|
* indicates stuck bits in the component reset register(stuck on or stuck off).
|
|
* If the value is 0xffffffff in CRR_results_20_0, then most likely the
|
|
* IO planar is not connected.
|
|
*/
|
|
int CRR_results_21_0; /* should contain 0x00000000 */
|
|
int CRR_results_21_a; /* should contain 0xaaaaaaaa */
|
|
int CRR_results_21_5; /* should contain 0x55555555 */
|
|
int CRR_results_21_f; /* should contain 0xffffffff */
|
|
|
|
/* This space reserved for future expansion for BUID 22, 23 CRR results */
|
|
int CRR_reserved[8];
|
|
/* int CRR_results_22_0; */
|
|
/* int CRR_results_22_a; */
|
|
/* int CRR_results_22_5; */
|
|
/* int CRR_results_22_f; */
|
|
/* int CRR_results_23_0; */
|
|
/* int CRR_results_23_a; */
|
|
/* int CRR_results_23_5; */
|
|
/* int CRR_results_23_f; */
|
|
|
|
/*
|
|
* IO INTERRUPT test results. For (OPTIONAL feature) BUID 21
|
|
* There are four data tests 0x00, 0xAA, 0x55 and 0xFF, when all tests are
|
|
* successful then the value found here will be zero. Any other value
|
|
* indicates failures during the interrupt test. A device connected to the
|
|
* the adapter in one of the IO slots could be causing the problem, or the
|
|
* IO planar is defective.
|
|
*/
|
|
int IO_INTERRUPT_results_21;
|
|
|
|
/* The following entries are reserved for IPL ROM usage.
|
|
* Pointer to a copy of the IPL ROM code in memory.
|
|
* The size of the IPL ROM code in memory.
|
|
*/
|
|
unsigned int *ROMs_RAM_address;
|
|
unsigned int ROMs_RAM_size;
|
|
|
|
/* The following entries are reserved for IPL ROM usage.
|
|
* Read the Storage Control Configuration Register.
|
|
* CONTROL BITS
|
|
* BIT_00 Diagnostic mode
|
|
* BIT_01 DMA Double Line
|
|
* BIT_02 and 03 Invert Address Bit (toggle one meg)
|
|
* bits 2 and 3 effect:
|
|
* 00 No effect, normal addressing.
|
|
* 01 Address bit 11 is inverted internally.
|
|
* 10 Address bit 10 is inverted internally.
|
|
* 11 Address bit 10 and 11 are both inverted internally.
|
|
* BIT_04 No holes in memory
|
|
*/
|
|
unsigned int SCCR_toggle_one_meg;
|
|
|
|
|
|
/* The following entry is read from the OCS NVRAM area
|
|
* See the comments of the model definition entry(AIX_model_code portion)
|
|
*/
|
|
unsigned int AIX_model_code; /* 4 bytes from NVRAM address 0xA0003d0 */
|
|
|
|
/* The following entries are read from the OCS NVRAM area
|
|
*
|
|
* ---------: dcache size = 0x0040 icache size = 0x0008
|
|
* ---------: dcache size = 0x0020 icache size = 0x0008
|
|
* ---------: dcache size = 0x0008 icache size = 0x0008
|
|
* ---------: dcache size = 0x0040 icache size = 0x0020
|
|
* ---------: dcache size = 0x0020 icache size = 0x0008
|
|
*/
|
|
int dcache_size; /* 4 bytes from NVRAM address 0xA0003d4 */
|
|
int icache_size; /* 4 bytes from NVRAM address 0xA0003d8 */
|
|
char vpd_Model_ID[8];
|
|
|
|
/* The following entry is reserved for IPL ROM usage.
|
|
* used to save the Pointer to the lowest address needed by IPL ROM in Memory.
|
|
* NOTE: this pointer is invalid when the value is -1.
|
|
*/
|
|
unsigned int *low_boundry_save;
|
|
|
|
/* The following entries is reserved for IPL ROM usage.
|
|
* Used to save the Pointer to the ROM Scan entry point and data area.
|
|
* NOTE: this pointer is invalid when the value is -1.
|
|
*/
|
|
int *ROM_SCAN_code_in_ram; /* runtime entry point of rom scan */
|
|
int *rom_boot_data_area; /* runtime user ram (4K or greater)*/
|
|
|
|
} IPL_INFO ;
|
|
#endif
|
|
#endif
|