347 lines
16 KiB
C
347 lines
16 KiB
C
/* @(#)82 1.7 src/bos/kernel/sys/POWER/system_rspc.h, sysios, bos41J, 9513A_all 3/23/95 17:39:57 */
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/*
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* COMPONENT_NAME: (SYSML) Kernel Machine Language
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*
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* FUNCTIONS:
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*
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* ORIGINS: 27
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*
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* (C) COPYRIGHT International Business Machines Corp. 1994, 1995
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* All Rights Reserved
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* Licensed Materials - Property of IBM
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*
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* US Government Users Restricted Rights - Use, duplication or
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* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
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*
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* This module contains in-line assembler functions for use by kernel.
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* These functions are for use by the base kernel only.
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*/
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#ifndef _H_SYSTEM_RSPC
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#define _H_SYSTEM_RSPC
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#ifdef _RSPC
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#define ISA0_IOSTART_SF 0x80000000
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/*
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* Defines for Dallas Semiconductor DS1385S RAMified Real time Clock
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*/
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#define RSPC_RTC_NMI 0x80
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/*
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* Defines for BUC Info Information in IPL Control Block
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*/
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/*
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* The following is the Device Characteristic defined for a device type
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* of bus bridge. This value is found in the device_type field of the
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* buc_info structure
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*/
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#define A_BUS_BRIDGE 5 /* Device Characteristics */
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/*
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* The following are the valid device IDs for device types of bus bridge.
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* These values are found in the device_id_reg field of the buc_info
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* structure
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*/
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#define PCI_BUS_ID 0x2010 /* PCI Bus */
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#define ISA_BUS_ID 0x2020 /* ISA Bus */
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#define PCMCIA_BUS_ID 0x2030 /* PCMCIA Bus */
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#define DMA_BUC_ID 0x2040 /* DMA Contiguous Buffer Info */
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#define HIBERNATION_BUC_ID 0x2050 /* Hibernation Wakeup Area Info */
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/*
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* SIO configuration registers, from 82378IB data sheet, rev 1.0, page 25
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*/
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struct sio_cfg {
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ushort vid; /* 0x00 vendor ID */
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ushort devid; /* 0x02 device ID */
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ushort cmd; /* 0x04 command */
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ushort status; /* 0x06 device status */
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char revision; /* 0x08 revision identifier */
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char res0[64-9]; /* 0x09 reserved */
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char pci_ctrl; /* 0x40 PCI control */
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char pci_arbit; /* 0x41 PCI arbiter control */
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char pci_arbit_pri; /* 0x42 PCI arbiter priority control */
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char res1; /* 0x43 reserved */
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char memcs_ctrl; /* 0x44 MEMCS# control */
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char memcs_bottom; /* 0x45 MEMCS# bottom of hole */
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char memcs_top; /* 0x46 MEMCS# top of hole */
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char memcs_memtop; /* 0x47 MEMCS# top of memory */
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char isa_ad_ctrl; /* 0x48 ISA AddressDecoder control */
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char isa_ad_rombe; /* 0x49 ISA AddressDecoder ROM block enable */
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char isa_ad_bottom; /* 0x4A ISA AddressDecoder bottom of hole */
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char isa_ad_top; /* 0x4B ISA AddressDecoder top of hole */
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char isa_crt; /* 0x4C ISA controller recovery timer */
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char isa_clk_div; /* 0x4D ISA clock divisor */
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char ubus_csela; /* 0x4E utility bus chip select enable A */
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char ubus_cselb; /* 0x4F utility bus chip select enable B */
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char res2[4]; /* 0x50 reserved */
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char memcs_attr[3]; /* 0x54 MEMCS# attribute register #1,#2,#3 */
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char sg_rba; /* 0x57 scatter/gather relocation base addr */
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char res3[0x80-0x58];/* 0x58 reserved */
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ushort bios_tba; /* 0x80 BIOS timer base address */
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char res4[0x100-0x82];/*0x82 reserved */
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};
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/*
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* RSPC SIO register definitions
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*/
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struct rspcsio {
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char dma1_ch0_bca; /* 0x000 DMA1 CH0 Base and Current Address */
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char dma1_ch0_bcc; /* 0x001 DMA1 CH0 Base and Current Count */
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char dma1_ch1_bca; /* 0x002 DMA1 CH1 Base and Current Address */
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char dma1_ch1_bcc; /* 0x003 DMA1 CH1 Base and Current Count */
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char dma1_ch2_bca; /* 0x004 DMA1 CH2 Base and Current Address */
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char dma1_ch2_bcc; /* 0x005 DMA1 CH2 Base and Current Count */
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char dma1_ch3_bca; /* 0x006 DMA1 CH3 Base and Current Address */
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char dma1_ch3_bcc; /* 0x007 DMA1 CH3 Base and Current Count */
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char dma1_dcom; /* 0x008 DMA1 command/status register */
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#define dma1_ds dma1_dcom /* 0x008 DMA1 status register */
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char dma1_req; /* 0x009 DMA1 Request register */
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char dma1_sm; /* 0x00A DMA1 Single Mask bit */
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char dma1_dcm; /* 0x00B DMA1 Mode register */
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char dma1_cbp; /* 0x00C DMA1 Clear Byte Pointer */
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char dma1_mclear; /* 0x00D DMA1 Master Clear */
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char dma1_cmask; /* 0x00E DMA1 Clear Mask */
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char dma1_amr; /* 0x00F DMA1 All Mask Register */
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char p0[0x20-0x10]; /* 0x010 padding */
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char int1_ctrl; /* 0x020 INT1 Control Register */
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char int1_mask; /* 0x021 INT1 Mask */
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char p1[0x40-0x22]; /* 0x022 padding */
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char tc1_count[3]; /* 0x040 TimerCounter1 Counter[0,1,2] Count */
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char tc1_mode; /* 0x043 TimerCounter1 Command Mode */
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char p2[0x60-0x44]; /* 0x044 padding */
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char rubus_irq12; /* 0x060 Reset UBus IRQ12 */
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char nmi_csr; /* 0x061 NMI control/status */
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char p3[0x70-0x62]; /* 0x062 padding */
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char rtc_index; /* 0x070 RTC Index register */
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char rtc_data; /* 0x071 RTC Data register */
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char p3a[0x74-0x72]; /* 0x072 padding */
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char nvram_ad_lo; /* 0x074 NVRAM Low address register */
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char nvram_ad_hi; /* 0x075 NVRAM High address register */
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char nvram_data_rspc;/* 0x076 NVRAM data port polo/woodfield */
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char nvram_data; /* 0x077 NVRAM data port sandalfoot */
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char p4[0x80-0x78]; /* 0x078 padding */
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char dma_page_res0; /* 0x080 DMA Page register (reserved) */
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char dma_page_ch2; /* 0x081 DMA Channel 2 Page register */
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char dma_page_ch3; /* 0x082 DMA Channel 3 Page register */
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char dma_page_ch1; /* 0x083 DMA Channel 1 Page register */
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char dma_page_res1; /* 0x084 DMA Page register (reserved) */
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char dma_page_res2; /* 0x085 DMA Page register (reserved) */
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char dma_page_res3; /* 0x086 DMA Page register (reserved) */
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char dma_page_ch0; /* 0x087 DMA Channel 0 Page register */
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char dma_page_res4; /* 0x088 DMA Page register (reserved) */
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char dma_page_ch6; /* 0x089 DMA Channel 6 Page register */
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char dma_page_ch7; /* 0x08A DMA Channel 7 Page register */
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char dma_page_ch5; /* 0x08B DMA Channel 5 Page register */
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char dma_page_res5; /* 0x08C DMA Page register (reserved) */
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char dma_page_res6; /* 0x08D DMA Page register (reserved) */
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char dma_page_res7; /* 0x08E DMA Page register (reserved) */
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char dma_lopage_ref0;/* 0x08F DMA low Page Refresh */
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char p5[2]; /* 0x090 padding */
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char ctl_scp; /* 0x092 CTL System Control Port */
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char p6[1]; /* 0x093 padding */
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char dma_page_res9; /* 0x094 DMA Page register (reserved) */
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char dma_page_res10; /* 0x095 DMA Page register (reserved) */
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char dma_page_res11; /* 0x096 DMA Page register (reserved) */
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char p7[1]; /* 0x097 padding */
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char dma_page_res12; /* 0x098 DMA Page register (reserved) */
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char p8[0x9c-0x99]; /* 0x099 padding */
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char dma_page_res13; /* 0x09C DMA Page register (reserved) */
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char dma_page_res14; /* 0x09D DMA Page register (reserved) */
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char dma_page_res15; /* 0x09E DMA Page register (reserved) */
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char dma_lopage_ref1;/* 0x09F DMA low Page Refresh */
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char int2_ctrl; /* 0x0A0 INT2 Control Register */
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char int2_mask; /* 0x0A1 INT2 Mask */
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char p9[0xc0-0xa2]; /* 0x0A2 padding */
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char dma2_ch0_bca; /* 0x0C0 DMA2 CH0 Base and Current Address */
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char pad0;
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char dma2_ch0_bcc; /* 0x0C2 DMA2 CH0 Base and Current Count */
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char pad1;
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char dma2_ch1_bca; /* 0x0C4 DMA2 CH1 Base and Current Address */
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char pad2;
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char dma2_ch1_bcc; /* 0x0C6 DMA2 CH1 Base and Current Count */
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char pad3;
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char dma2_ch2_bca; /* 0x0C8 DMA2 CH2 Base and Current Address */
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char pad4;
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char dma2_ch2_bcc; /* 0x0CA DMA2 CH2 Base and Current Count */
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char pad5;
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char dma2_ch3_bca; /* 0x0CC DMA2 CH3 Base and Current Address */
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char pad6;
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char dma2_ch3_bcc; /* 0x0CE DMA2 CH3 Base and Current Count */
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char pad7;
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char dma2_dcom; /* 0x0D0 DMA2 command register */
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#define dma2_ds dma2_dcom /* 0x0D0 DMA2 status register */
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char pad8;
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char dma2_req; /* 0x0D2 DMA2 Request register */
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char pad9;
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char dma2_sm; /* 0x0D4 DMA2 Single Mask bit */
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char pada;
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char dma2_dcm; /* 0x0D6 DMA2 Mode register */
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char padb;
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char dma2_cbp; /* 0x0D8 DMA2 Clear Byte Pointer */
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char padc;
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char dma2_mclear; /* 0x0DA DMA2 Master Clear */
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char padd;
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char dma2_cmask; /* 0x0DC DMA2 Clear Mask */
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char pade;
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char dma2_amr; /* 0x0DE DMA2 All Mask Register */
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char padf;
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char pa[0xf0-0xe0]; /* 0x0E0 padding */
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char coproc_err; /* 0x0F0 Coprocessor Error */
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char pb[0x372-0xf1];
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char sec_fddor; /* 0x372 Secondary FloppyDiskDigitalOutputReg*/
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char pc[0x3f2-0x373];
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char pri_fddor; /* 0x3F2 Primary FloppyDiskDigitalOutputReg */
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char pd[0x40b-0x3f3];
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char dma1_dcem; /* 0x40B DMA1 Extended Mode */
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char pe[0x410-0x40c];
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char dma_sg_cmd[8]; /* 0x410 DMA Scatter/Gather Command */
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char dma_sg_stat[8]; /* 0x418 DMA Scatter/Gather Status */
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ulong dma_sg_dtp[8]; /* 0x420 DMA Scatter/Gather DescriptorTblPtr */
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char pf[0x481-0x440];
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char dma_hipage_ch2; /* 0x481 DMA CH2 High Page register */
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char dma_hipage_ch3; /* 0x482 DMA CH3 High Page register */
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char dma_hipage_ch1; /* 0x483 DMA CH1 High Page register */
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char pad10[3];
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char dma_hipage_ch0; /* 0x487 DMA CH0 High Page register */
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char pad11;
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char dma_hipage_ch6; /* 0x489 DMA CH6 High Page register */
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char dma_hipage_ch7; /* 0x48A DMA CH7 High Page register */
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char dma_hipage_ch5; /* 0x48B DMA CH5 High Page register */
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char pg[0x4d6-0x48c];
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char dma2_dcem; /* 0x4D6 DMA2 Extended Mode */
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};
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/*
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* Scatter/Gather Command register bits
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*/
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#define SGC_EOP (3 << 6) /* EOP asserted when io done */
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#define SGC_IRQ13 (1 << 6) /* IRQ13 asserted when io done */
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#define SGC_NOP (0 << 0) /* No S/G operation */
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#define SGC_START (1 << 0) /* Start S/G command */
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#define SGC_STOP (2 << 0) /* Stop S/G command */
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/* Define 8259 interrupt controller stuff */
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/* Diagram of how the 8259s are logically connected
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MASTER
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+----------+
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INT line to processor <----| |<-- IRQ0 SLAVE
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| |<-- IRQ1 +----------+
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| |<-- IRQ2 -----| |<-- IRQ 8
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| |<-- IRQ3 | |<-- IRQ 9
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| |<-- IRQ4 | |<-- IRQ 10
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| |<-- IRQ5 | |<-- IRQ 11
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| |<-- IRQ6 | |<-- IRQ 12
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| |<-- IRQ7 | |<-- IRQ 13
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+----------+ | |<-- IRQ 14
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| |<-- IRQ 15
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+----------+
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*
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* Mask data to/from a 8259 is as follows
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*
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+-- IRQ 6 & 14 +-- IRQ 1 & 9
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+-------------------------------+
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| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
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+-------------------------------+
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+-- IRQ 7 & 15 +-- IRQ 0 & 8
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*/
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/* Important addresses */
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#define INTA00 0x20 /* 8259 master control port address */
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#define INTA01 0x21 /* 8259 master mask port */
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#define INTB00 0xA0 /* 8259 slave control port address */
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#define INTB01 0xA1 /* 8259 slave mask port */
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#define ELCR0 0x04D0 /* IRQ 0-7 Edge/Level control register */
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#define ELCR1 0x04D1 /* IRQ 8-15 Edge/Level control register */
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#define RSPCINT_VECT 0xBFFFFFF0 /* Address of IVR register */
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#define CASCADE_IRQ 4 /* Value used to indicate which IRQ line*/
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/* on the master the slave is attached */
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/* to. */
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/* Initialization words for both controllers */
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/* ICW1 */
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/* - ICW/OCW = 1 ICW select must be a 1 for ICW1 */
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/* - LTIM = 0 Edge triggered(not used on 82378ZB) */
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/* - ADI = 1 Interval = 4(ingnored on 82378ZB) */
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/* - SNGL = 0 Multiple 8259 controllers in the system */
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/* - ICA = 1 Sending ICW4(must be a 1 on 82378ZB) */
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#define ICW1 0x15
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/* ICW2A - Master interrupts are numbered from 0 to 7 */
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#define ICW2A 0x00
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/* ICW2B - Slave interrupts are numbered from 8 to 15 */
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#define ICW2B 0x08
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/* ICW3A (Note that pin 16(SP) is logical 1 on this chip = MASTER */
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/* - Slave is on IRQ 2 (pin 20) */
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#define ICW3A 0x04
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/* ICW3B (Note that pin 16(SP) is logical 0 on this chip = SLAVE */
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/* - Slave id is 2 (See hardware book for table) */
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#define ICW3B 0x02
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/* ICW4 */
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/* - SFNM = 0 Special fully nested mode is NOT programmed */
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/* - BUF = 0 Buffered mode is NOT programmed (SP, pin 16, selects master)*/
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/* - M/S = 0 Ignored unless BUF=1, which it doesn't */
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/* - AEOI = 0 Automatic end of interrupt(EOI) is NOT programmed */
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/* - uPM = 1 MCS-86 operation is programmed (only 1 status byte) */
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#define ICW4 0x01
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/* OCW3 command encodings */
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#define OCW3_GETIRR 0x0A
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#define OCW3_GETISR 0x0B
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/* Generate a IMR mask(value) for 8259 IMR register */
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#define I8259_IMR_MSK( Lvl ) ((ulong)((ulong)(0x00000001) << (Lvl) ))
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/* The interrupt we are gating here is NMI. It generates a machine check. */
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#define NMISC 0x61 /* NMI Status and Control Register */
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#define NMI_SBE 0x80 /* R/O: System board detected error */
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#define NMI_SRC 0x40 /* R/O: IOCHK from ISA bus error */
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#define NMI_C2OUT 0x20 /* R/O: Current status of TIMER2 output */
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#define NMI_RFRSH 0x10 /* R/O: Refresh stuff */
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#define NMI_SRCOK 0x08 /* R/W: IOCHK interrupt enable */
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#define NMI_SBEOK 0x04 /* R/W: System board(+PCI) interrupt ok */
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#define NMI_SPKOK 0x02 /* R/W: Speaker output from TIMER2 ok */
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#define NMI_T2ENA 0x01 /* R/W: Enable TIMER2 counting */
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#define NMISC_INIT (NMI_SRCOK | NMI_SBEOK)
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#define NMIREG 0x70 /* NMI Enable and Real-Time Clock Addr */
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#define NMI_OK 0x80 /* NMI enable (0==enable, default==1) */
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#define NMIREG_INIT 0x00 /* Enable NMI interrupts */
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#endif /* _RSPC */
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#endif /* _H_SYSTEM_RSPC */
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