167 lines
5.6 KiB
C
167 lines
5.6 KiB
C
/* @(#)29 1.5 src/bos/kernel/sys/POWER/systemcfg.h, sysml, bos411, 9428A410j 3/20/94 21:33:34 */
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#ifndef _H_SYSTEMCFG
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#define _H_SYSTEMCFG
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/*
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* COMPONENT_NAME: (SYSML) Kernel Machine Language
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*
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* FUNCTIONS: System Characteristics Identification
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*
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* ORIGINS: 27, 83
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*
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* (C) COPYRIGHT International Business Machines Corp. 1992, 1994
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* All Rights Reserved
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* Licensed Materials - Property of IBM
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*
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* US Government Users Restricted Rights - Use, duplication or
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* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
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*/
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/*
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* LEVEL 1, 5 Years Bull Confidential Information
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*/
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/*
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* WARNINGS:
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* The size of this structure will grow in future releases
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*
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* Do not make this structure larger than 64 words
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*
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* Do not update without changing systemcfg.m4 and ufcp.m4
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*/
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extern struct {
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int architecture; /* processor architecture */
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int implementation; /* processor implementation */
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int version; /* processor version */
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int width; /* width (32 || 64) */
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int ncpus; /* 1 = UP, n = n-way MP */
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int cache_attrib; /* cache attributes (bit flags) */
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/* bit 0/1 meaning */
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/* -------------------------------------*/
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/* 31 no cache / cache present */
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/* 30 separate I and D / combined */
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int icache_size; /* size of L1 instruction cache */
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int dcache_size; /* size of L1 data cache */
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int icache_asc; /* L1 instruction cache associativity */
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int dcache_asc; /* L1 data cache associativity */
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int icache_block; /* L1 instruction cache block size */
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int dcache_block; /* L1 data cache block size */
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int icache_line; /* L1 instruction cache line size */
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int dcache_line; /* L1 data cache line size */
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int L2_cache_size; /* size of L2 cache, 0 = No L2 cache */
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int L2_cache_asc; /* L2 cache associativity */
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int tlb_attrib; /* TLB attributes (bit flags) */
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/* bit 0/1 meaning */
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/* -------------------------------------*/
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/* 31 no TLB / TLB present */
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/* 30 separate I and D / combined */
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int itlb_size; /* entries in instruction TLB */
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int dtlb_size; /* entries in data TLB */
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int itlb_asc; /* instruction tlb associativity */
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int dtlb_asc; /* data tlb associativity */
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int resv_size; /* size of reservation */
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int priv_lck_cnt; /* spin lock count in supevisor mode */
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int prob_lck_cnt; /* spin lock count in problem state */
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int rtc_type; /* RTC type */
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int virt_alias; /* 1 if hardware aliasing is supported */
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int cach_cong; /* number of page bits for cache synonym */
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int model_arch; /* used by system for model determination */
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int model_impl; /* used by system for model determination */
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int Xint; /* used by system for time base conversion */
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int Xfrac; /* used by system for time base conversion */
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}_system_configuration;
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/* Values for architecture field
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*/
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#define POWER_RS 0x0001 /* Power Classic architecture */
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#define POWER_PC 0x0002 /* Power PC architecture */
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/* Values for implementation field
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*/
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#define POWER_RS1 0x0001 /* RS1 class CPU */
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#define POWER_RSC 0x0002 /* RSC class CPU */
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#define POWER_RS2 0x0004 /* RS2 class CPU */
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#define POWER_601 0x0008 /* 601 class CPU */
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#define POWER_603 0x0020 /* 603 class CPU */
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#define POWER_604 0x0010 /* 604 class CPU */
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#define POWER_620 0x0040 /* 620 class CPU */
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/* Sets of implementations
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*/
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#define POWER_RS_ALL (POWER_RS1|POWER_RSC|POWER_RS2)
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#define POWER_PC_ALL (POWER_601|POWER_603|POWER_604|POWER_620)
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/* Values for the version field
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*/
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#define PV_601 0x10001 /* Power PC 601 */
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#define PV_601a 0x10002 /* Power PC 601 */
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#define PV_603 0x60000 /* Power PC 603 */
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#define PV_604 0x50000 /* Power PC 604 */
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#define PV_620 0x70000 /* Power PC 620 */
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#define PV_RS2 0x40000 /* Power RS2 */
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#define PV_RS1 0x20000 /* Power RS1 */
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#define PV_RSC 0x30000 /* Power RSC */
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/* Values for rtc_type
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*/
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#define RTC_POWER 1 /* rtc as defined by Power Arch. */
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#define RTC_POWER_PC 2 /* rtc as defined by Power PC Arch. */
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/* macros for runtime architecture and implementation checks
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*/
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#define __power_rs() (_system_configuration.architecture == POWER_RS)
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#define __power_pc() (_system_configuration.architecture == POWER_PC)
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#define __power_set(a) (_system_configuration.implementation & (a))
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#define __power_mp() (_system_configuration.ncpus > 1)
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#define __power_rs1() (_system_configuration.implementation == POWER_RS1)
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#define __power_rsc() (_system_configuration.implementation == POWER_RSC)
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#define __power_rs2() (_system_configuration.implementation == POWER_RS2)
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#define __power_601() (_system_configuration.implementation == POWER_601)
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#define __power_603() (_system_configuration.implementation == POWER_603)
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#define __power_604() (_system_configuration.implementation == POWER_604)
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#define __power_620() (_system_configuration.implementation == POWER_620)
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#ifdef _KERNSYS
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/* Defines and macros for model specific checks. These are intended for
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* internal use only. There is no guarantee made how these function on
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* new models
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*/
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#ifdef _RS6K
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#define RS6K 1
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#define __rs6k() (_system_configuration.model_arch == RS6K)
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#else
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#define __rs6k() 0
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#endif
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#ifdef _RSPC
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#define RSPC 2
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#define __rspc() (_system_configuration.model_arch == RSPC)
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#else
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#define __rspc() 0
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#endif
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#ifdef _RS6K_UP_MCA
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#define RS6K_UP_MCA 1
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#define __rs6k_up_mca() (_system_configuration.model_impl == RS6K_UP_MCA)
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#else
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#define __rs6k_up_mca() 0
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#endif
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#ifdef _RS6K_SMP_MCA
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#define RS6K_SMP_MCA 2
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#define __rs6k_smp_mca() (_system_configuration.model_impl == RS6K_SMP_MCA)
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#else
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#define __rs6k_smp_mca() 0
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#endif
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#ifdef _RSPC_UP_PCI
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#define RSPC_UP_PCI 3
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#define __rspc_up_pci() (_system_configuration.model_impl == RSPC_UP_PCI)
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#else
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#define __rspc_up_pci() 0
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#endif
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#endif /* _KERNSYS */
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#endif /* _H_SYSTEMCFG */
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