352 lines
13 KiB
C
Executable File
352 lines
13 KiB
C
Executable File
/*
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* Copyright (c) 1994, 1995 by Sun Microsystems, Inc.
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*/
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#ifndef _SYS_PCI_H
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#define _SYS_PCI_H
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#pragma ident "@(#)pci.h 1.11 95/09/22 SMI"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* PCI Configuration Header offsets
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*/
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#define PCI_CONF_VENID 0x0 /* vendor id, 2 bytes */
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#define PCI_CONF_DEVID 0x2 /* device id, 2 bytes */
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#define PCI_CONF_COMM 0x4 /* command register, 2 bytes */
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#define PCI_CONF_STAT 0x6 /* status register, 2 bytes */
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#define PCI_CONF_REVID 0x8 /* revision id, 1 byte */
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#define PCI_CONF_PROGCLASS 0x9 /* programming class code, 1 byte */
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#define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */
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#define PCI_CONF_BASCLASS 0xB /* basic class code, 1 byte */
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#define PCI_CONF_CACHE_LINESZ 0xC /* cache line size, 1 byte */
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#define PCI_CONF_LATENCY_TIMER 0xD /* latency timer, 1 byte */
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#define PCI_CONF_HEADER 0xE /* header type, 1 byte */
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#define PCI_CONF_BIST 0xF /* builtin self test, 1 byte */
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#define PCI_CONF_BASE0 0x10 /* base register 0, 4 bytes */
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#define PCI_CONF_BASE1 0x14 /* base register 1, 4 bytes */
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#define PCI_CONF_BASE2 0x18 /* base register 2, 4 bytes */
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#define PCI_CONF_BASE3 0x1c /* base register 3, 4 bytes */
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#define PCI_CONF_BASE4 0x20 /* base register 4, 4 bytes */
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#define PCI_CONF_BASE5 0x24 /* base register 5, 4 bytes */
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#define PCI_CONF_CIS 0x28 /* Cardbus CIS Pointer */
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#define PCI_CONF_SUBVENID 0x2c /* Subsystem Vendor ID */
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#define PCI_CONF_SUBSYSID 0x2e /* Subsystem ID */
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#define PCI_CONF_ROM 0x30 /* ROM base register, 4 bytes */
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#define PCI_CONF_ILINE 0x3c /* interrupt line, 1 byte */
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#define PCI_CONF_IPIN 0x3d /* interrupt pin, 1 byte */
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#define PCI_CONF_MIN_G 0x3e /* minimum grant, 1 byte */
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#define PCI_CONF_MAX_L 0x3f /* maximum grant, 1 byte */
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/*
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* PCI to PCI bridge configuration space header format
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*/
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#define PCI_BCNF_PRIBUS 0x18 /* primary bus number */
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#define PCI_BCNF_SECBUS 0x19 /* secondary bus number */
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#define PCI_BCNF_SUBBUS 0x1a /* subordinate bus number */
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/*
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* PCI command register bits
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*/
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#define PCI_COMM_IO 0x0001 /* I/O access enable */
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#define PCI_COMM_MAE 0x0002 /* memory access enable */
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#define PCI_COMM_ME 0x0004 /* master enable */
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#define PCI_COMM_SPEC_CYC 0x0008
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#define PCI_COMM_MEMWR_INVAL 0x0010
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#define PCI_COMM_PALETTE_SNOOP 0x0020
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#define PCI_COMM_PARITY_DETECT 0x0040
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#define PCI_COMM_WAIT_CYC_ENAB 0x0080
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#define PCI_COMM_SERR_ENABLE 0x0100
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#define PCI_COMM_BACK2BACK_ENAB 0x0200
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/*
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* PCI Interrupt pin value
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*/
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#define PCI_INTA 1
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#define PCI_INTB 2
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#define PCI_INTC 3
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#define PCI_INTD 4
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/*
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* PCI status register bits
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*/
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#define PCI_STAT_66MHZ 0x0020 /* 66 MHz capable */
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#define PCI_STAT_UDF 0x0040 /* UDF supported */
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#define PCI_STAT_FBBC 0x0080 /* Fast Back-to-Back Capable */
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#define PCI_STAT_S_PERROR 0x0100 /* Data Parity Reported */
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#define PCI_STAT_DEVSELT 0x0600 /* Device select timing */
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#define PCI_STAT_S_TARG_AB 0x0800 /* Signaled Target Abort */
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#define PCI_STAT_R_TARG_AB 0x1000 /* Received Target Abort */
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#define PCI_STAT_R_MAST_AB 0x2000 /* Received Master Abort */
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#define PCI_STAT_S_SYSERR 0x4000 /* Signaled System Error */
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#define PCI_STAT_PERROR 0x8000 /* Detected Parity Error */
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/*
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* PCI class codes
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*/
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#define PCI_CLASS_NONE 0x0 /* class code for pre-2.0 devices */
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#define PCI_CLASS_MASS 0x1 /* Mass storage Controller class */
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#define PCI_CLASS_NET 0x2 /* Network Controller class */
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#define PCI_CLASS_DISPLAY 0x3 /* Display Controller class */
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#define PCI_CLASS_MM 0x4 /* Multimedia Controller class */
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#define PCI_CLASS_MEM 0x5 /* Memory Controller class */
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#define PCI_CLASS_BRIDGE 0x6 /* Bridge Controller class */
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#define PCI_CLASS_COMM 0x7 /* Communications Controller class */
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#define PCI_CLASS_PERIPH 0x8 /* Peripheral Controller class */
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#define PCI_CLASS_INPUT 0x9 /* Input Device class */
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#define PCI_CLASS_DOCK 0xa /* Docking Station class */
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#define PCI_CLASS_PROCESSOR 0xb /* Processor class */
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#define PCI_CLASS_SERIALBUS 0xc /* Serial Bus class */
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/*
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* PCI Sub-class codes - base class 0x0 (no new devices should use this code).
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*/
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#define PCI_NONE_NOTVGA 0x0 /* All devices except VGA compatible */
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#define PCI_NONE_VGA 0x1 /* VGA compatible */
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/*
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* PCI Sub-class codes - base class 0x1
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*/
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#define PCI_MASS_SCSI 0x0 /* SCSI bus Controller */
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#define PCI_MASS_IDE 0x1 /* IDE Controller */
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#define PCI_MASS_FD 0x2 /* floppy disk Controller */
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#define PCI_MASS_IPI 0x3 /* IPI bus Controller */
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#define PCI_MASS_RAID 0x4 /* RAID Controller */
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#define PCI_MASS_OTHER 0x80 /* Other Mass Storage Controller */
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/*
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* programming interface for IDE
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*/
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#define PCI_IDE_IF_NATIVE_PRI 0x01 /* primary channel is native */
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#define PCI_IDE_IF_PROG_PRI 0x02 /* primary can operate in either mode */
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#define PCI_IDE_IF_NATIVE_SEC 0x04 /* secondary channel is native */
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#define PCI_IDE_IF_PROG_SEC 0x08 /* sec. can operate in either mode */
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#define PCI_IDE_IF_MASK 0x0f /* programming interface mask */
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/*
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* PCI Sub-class codes - base class 0x2
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*/
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#define PCI_NET_ENET 0x0 /* Ethernet Controller */
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#define PCI_NET_TOKEN 0x1 /* Token Ring Controller */
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#define PCI_NET_FDDI 0x2 /* FDDI Controller */
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#define PCI_NET_ATM 0x3 /* ATM Controller */
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#define PCI_NET_OTHER 0x80 /* Other Network Controller */
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/*
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* PCI Sub-class codes - base class 0x3
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*/
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#define PCI_DISPLAY_VGA 0x0 /* VGA device */
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#define PCI_DISPLAY_XGA 0x1 /* XGA device */
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#define PCI_DISPLAY_OTHER 0x80 /* Other Display Device */
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/*
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* programming interface for display
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*/
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#define PCI_DISPLAY_IF_VGA 0x0b /* VGA compatible */
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#define PCI_DISPLAY_IF_8514 0x1b /* 8514 compatible */
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/*
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* PCI Sub-class codes - base class 0x4
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*/
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#define PCI_MM_VIDEO 0x0 /* Video device */
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#define PCI_MM_AUDIO 0x1 /* Audio device */
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#define PCI_MM_OTHER 0x80 /* Other Multimedia Device */
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/*
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* PCI Sub-class codes - base class 0x5
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*/
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#define PCI_MEM_RAM 0x0 /* RAM device */
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#define PCI_MEM_FLASH 0x1 /* FLASH device */
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#define PCI_MEM_OTHER 0x80 /* Other Memory Controller */
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/*
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* PCI Sub-class codes - base class 0x6
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*/
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#define PCI_BRIDGE_HOST 0x0 /* Host/PCI Bridge */
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#define PCI_BRIDGE_ISA 0x1 /* PCI/ISA Bridge */
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#define PCI_BRIDGE_EISA 0x2 /* PCI/EISA Bridge */
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#define PCI_BRIDGE_MC 0x3 /* PCI/MC Bridge */
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#define PCI_BRIDGE_PCI 0x4 /* PCI/PCI Bridge */
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#define PCI_BRIDGE_PCMCIA 0x5 /* PCI/PCMCIA Bridge */
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#define PCI_BRIDGE_NUBUS 0x6 /* PCI/NUBUS Bridge */
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#define PCI_BRIDGE_CARDBUS 0x7 /* PCI/CARDBUS Bridge */
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#define PCI_BRIDGE_OTHER 0x80 /* PCI/Other Bridge Device */
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/*
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* PCI Sub-class codes - base class 0x7
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*/
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#define PCI_COMM_GENERIC_XT 0x0 /* XT Compatible Serial Controller */
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#define PCI_COMM_PARALLEL 0x1 /* Parallel Port Controller */
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#define PCI_COMM_OTHER 0x80 /* Other Communications Controller */
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/*
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* PCI Sub-class codes - base class 0x8
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*/
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#define PCI_PERIPH_PIC 0x0 /* Generic PIC */
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#define PCI_PERIPH_DMA 0x1 /* Generic DMA Controller */
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#define PCI_PERIPH_TIMER 0x2 /* Generic System Timer Controller */
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#define PCI_PERIPH_RTC 0x3 /* Generic RTC Controller */
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#define PCI_PERIPH_OTHER 0x80 /* Other System Peripheral */
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/*
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* PCI Sub-class codes - base class 0x9
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*/
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#define PCI_INPUT_KEYBOARD 0x0 /* Keyboard Controler */
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#define PCI_INPUT_DIGITIZ 0x1 /* Digitizer (Pen) */
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#define PCI_INPUT_MOUSE 0x2 /* Mouse Controller */
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#define PCI_INPUT_OTHER 0x80 /* Other Input Controller */
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/*
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* PCI Sub-class codes - base class 0xa
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*/
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#define PCI_DOCK_GENERIC 0x0 /* Generic Docking Station */
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#define PCI_DOCK_OTHER 0x80 /* Other Type of Docking Station */
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/*
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* PCI Sub-class codes - base class 0xb
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*/
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#define PCI_PROCESSOR_386 0x0 /* 386 */
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#define PCI_PROCESSOR_486 0x1 /* 486 */
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#define PCI_PROCESSOR_PENT 0x2 /* Pentium */
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#define PCI_PROCESSOR_ALPHA 0x10 /* Alpha */
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#define PCI_PROCESSOR_COPROC 0x40 /* Co-processor */
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/*
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* PCI Sub-class codes - base class 0xc
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*/
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#define PCI_SERIAL_FIRE 0x0 /* FireWire (IEEE 1394) */
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#define PCI_SERIAL_ACCESS 0x1 /* ACCESS.bus */
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#define PCI_SERIAL_SSA 0x2 /* SSA */
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/* PCI header decode */
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#define PCI_HEADER_MULTI 0x80 /* multi-function device */
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#define PCI_HEADER_ZERO 0x00 /* type zero PCI header */
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#define PCI_HEADER_ONE 0x01 /* type one PCI header */
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#define PCI_HEADER_PPB PCI_HEADER_ONE /* type one PCI to PCI Bridge */
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#define PCI_HEADER_TYPE_M 0x3f /* type mask for header */
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/*
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* Base register bit definitions.
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*/
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#define PCI_BASE_SPACE_M 0x00000001 /* memory space indicator */
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#define PCI_BASE_SPACE_IO 0x1 /* IO space */
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#define PCI_BASE_SPACE_MEM 0x0 /* memory space */
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#define PCI_BASE_TYPE_MEM 0x0 /* 32-bit memory address */
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#define PCI_BASE_TYPE_LOW 0x2 /* less than 1Mb address */
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#define PCI_BASE_TYPE_ALL 0x4 /* 64-bit memory address */
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#define PCI_BASE_TYPE_RES 0x6 /* reserved */
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#define PCI_BASE_TYPE_M 0x00000006 /* type indicator mask */
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#define PCI_BASE_PREF_M 0x00000008 /* prefetch mask */
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#define PCI_BASE_M_ADDR_M 0xfffffff0 /* memory address mask */
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#define PCI_BASE_IO_ADDR_M 0xfffffffe /* I/O address mask */
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/* XXX need command and status definitions */
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/*
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* This structure represents one entry of the 1275 "reg" property and
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* "assigned-addresses" property for a PCI node. For the "reg" property, it
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* may be one of an arbitrary length array for devices with multiple address
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* windows. For the "assigned-addresses" property, it denotes an assigned
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* physical address on the PCI bus. It may be one entry of the six entries
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* for devices with multiple base registers.
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*
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* The physical address format is:
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*
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* Bit#: 33222222 22221111 11111100 00000000
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* 10987654 32109876 54321098 76543210
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*
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* pci_phys_hi cell: np0000tt bbbbbbbb dddddfff rrrrrrrr
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* pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
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* pci_phys_low cell: llllllll llllllll llllllll llllllll
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*
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* n is 0 if the address is relocatable, 1 otherwise
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* p is 1 if the addressable region is "prefetchable", 0 otherwise
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* t is 1 if the address range is aliased
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* tt is the type code, denoting which address space
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* bbbbbbbb is the 8-bit bus number
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* ddddd is the 5-bit device number
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* fff is the 3-bit function number
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* rrrrrrrr is the 8-bit register number
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* hh...hhh is the 32-bit unsigned number
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* ll...lll is the 32-bit unsigned number
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*
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* The physical size format is:
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*
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* pci_size_hi cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
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* pci_size_low cell: llllllll llllllll llllllll llllllll
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*
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* hh...hhh is the 32-bit unsigned number
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* ll...lll is the 32-bit unsigned number
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*/
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struct pci_phys_spec {
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u_int pci_phys_hi; /* child's address, hi word */
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u_int pci_phys_mid; /* child's address, middle word */
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u_int pci_phys_low; /* child's address, low word */
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u_int pci_size_hi; /* high word of size field */
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u_int pci_size_low; /* low word of size field */
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};
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typedef struct pci_phys_spec pci_regspec_t;
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/*
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* PCI masks for pci_phy_hi of PCI 1275 address cell.
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*/
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#define PCI_REG_REG_M 0x000000ff /* register mask */
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#define PCI_REG_FUNC_M 0x00000700 /* function mask */
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#define PCI_REG_DEV_M 0x0000f800 /* device mask */
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#define PCI_REG_BUS_M 0x00ff0000 /* bus number mask */
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#define PCI_REG_ADDR_M 0x03000000 /* address space mask */
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#define PCI_REG_ALIAS_M 0x20000000 /* aliased bit mask */
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#define PCI_REG_PF_M 0x40000000 /* prefetch bit mask */
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#define PCI_REG_REL_M 0x80000000 /* relocation bit mask */
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#define PCI_REG_REG_G(x) (x & PCI_REG_REG_M)
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#define PCI_REG_FUNC_G(x) ((x & PCI_REG_FUNC_M) >> 8)
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#define PCI_REG_DEV_G(x) ((x & PCI_REG_DEV_M) >> 11)
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#define PCI_REG_BUS_G(x) ((x & PCI_REG_BUS_M) >> 16)
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#define PCI_REG_ADDR_G(x) ((x & PCI_REG_ADDR_M) >> 24)
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/*
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* PCI bit encodings of pci_phy_hi of PCI 1275 address cell.
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*/
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#define PCI_ADDR_MASK 0x03000000 /* configuration address */
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#define PCI_ADDR_CONFIG 0x00000000 /* configuration address */
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#define PCI_ADDR_IO 0x01000000 /* I/O address */
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#define PCI_ADDR_MEM32 0x02000000 /* 32-bit memory address */
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#define PCI_ADDR_MEM64 0x03000000 /* 64-bit memory address */
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#define PCI_ALIAS_B 0x20000000 /* aliased bit */
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#define PCI_PREFETCH_B 0x40000000 /* prefetch bit */
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#define PCI_RELOCAT_B 0x80000000 /* relocatable bit */
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#define PCI_CONF_ADDR_MASK 0x00ffffff /* mask for config address */
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/*
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* other interesting PCI constants
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*/
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#define PCI_BASE_NUM 6 /* num of base regs in configuration header */
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#define PCI_BASE_SIZE 4 /* size of base reg in bytes */
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#define PCI_CONF_HDR_SIZE 256 /* configuration header size */
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#define PCI_HARDDEC_8514 2 /* number of reg entries for 8514 hard-decode */
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#define PCI_HARDDEC_VGA 3 /* number of reg entries for VGA hard-decode */
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#define PCI_HARDDEC_IDE 4 /* number of reg entries for IDE hard-decode */
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#define PCI_HARDDEC_IDE_PRI 2 /* number of reg entries for IDE primary */
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#define PCI_HARDDEC_IDE_SEC 2 /* number of reg entries for IDE secondary */
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/*
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* PCI to PCI bus bridge
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*/
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#define PCI_PPB_ROM 0x38 /* expansion ROM base address */
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#define PCI_PPB_BASE_NUM 0x2 /* number of base registers */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SYS_PCI_H */
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