186 lines
5.1 KiB
C
Executable File
186 lines
5.1 KiB
C
Executable File
/*
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* Copyright (c) 1990, by Sun Microsystems, Inc.
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*/
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#ifndef _SYS_CPU_H
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#define _SYS_CPU_H
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#pragma ident "@(#)cpu.h 1.16 93/04/22 SMI"
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/*
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* This file contains common identification and reference information
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* for all sparc-based kernels.
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*
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* Coincidentally, the arch and mach fields that uniquely identifies
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* a cpu is what is stored in either nvram or idprom for a platform.
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* XXX: This may change!
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*/
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/*
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* Include generic bustype cookies.
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*/
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#include <sys/bustypes.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CPU_ARCH 0xf0 /* mask for architecture bits */
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#define CPU_MACH 0x0f /* mask for machine implementation */
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#define CPU_ANY (CPU_ARCH|CPU_MACH)
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#define CPU_NONE 0
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/*
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* sun4 architectures
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*/
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#define SUN4_ARCH 0x20 /* arch value for Sun 4 */
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#define SUN4_MACH_260 0x01
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#define SUN4_MACH_110 0x02
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#define SUN4_MACH_330 0x03
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#define SUN4_MACH_470 0x04
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#define CPU_SUN4_260 (SUN4_ARCH + SUN4_MACH_260)
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#define CPU_SUN4_110 (SUN4_ARCH + SUN4_MACH_110)
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#define CPU_SUN4_330 (SUN4_ARCH + SUN4_MACH_330)
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#define CPU_SUN4_470 (SUN4_ARCH + SUN4_MACH_470)
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#define CPU_SUN4 (SUN4_ARCH + CPU_MACH)
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/*
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* sun4c architectures
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*/
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#define SUN4C_ARCH 0x50 /* arch value for Sun 4c */
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#define SUN4C_MACH_60 0x01 /* SPARCstation 1 */
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#define SUN4C_MACH_40 0x02 /* SPARCstation IPC */
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#define SUN4C_MACH_65 0x03 /* SPARCstation 1+ */
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#define SUN4C_MACH_20 0x04 /* SPARCstation SLC */
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#define SUN4C_MACH_75 0x05 /* SPARCstation 2 */
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#define SUN4C_MACH_25 0x06 /* SPARCstation ELC */
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#define SUN4C_MACH_50 0x07 /* SPARCstation IPX */
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#define SUN4C_MACH_70 0x08
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#define SUN4C_MACH_80 0x09
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#define SUN4C_MACH_10 0x0a
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#define SUN4C_MACH_45 0x0b
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#define SUN4C_MACH_05 0x0c
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#define SUN4C_MACH_85 0x0d
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#define SUN4C_MACH_32 0x0e
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#define CPU_SUN4C_60 (SUN4C_ARCH + SUN4C_MACH_60)
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#define CPU_SUN4C_40 (SUN4C_ARCH + SUN4C_MACH_40)
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#define CPU_SUN4C_65 (SUN4C_ARCH + SUN4C_MACH_65)
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#define CPU_SUN4C_20 (SUN4C_ARCH + SUN4C_MACH_20)
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#define CPU_SUN4C_75 (SUN4C_ARCH + SUN4C_MACH_75)
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#define CPU_SUN4C_25 (SUN4C_ARCH + SUN4C_MACH_25)
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#define CPU_SUN4C_50 (SUN4C_ARCH + SUN4C_MACH_50)
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#define CPU_SUN4C_70 (SUN4C_ARCH + SUN4C_MACH_70)
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#define CPU_SUN4C_80 (SUN4C_ARCH + SUN4C_MACH_80)
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#define CPU_SUN4C_10 (SUN4C_ARCH + SUN4C_MACH_10)
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#define CPU_SUN4C_45 (SUN4C_ARCH + SUN4C_MACH_45)
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#define CPU_SUN4C_05 (SUN4C_ARCH + SUN4C_MACH_05)
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#define CPU_SUN4C_85 (SUN4C_ARCH + SUN4C_MACH_85)
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#define CPU_SUN4C_32 (SUN4C_ARCH + SUN4C_MACH_32)
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#define CPU_SUN4C (SUN4C_ARCH + CPU_MACH)
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/*
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* sun4e architectures
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*/
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#define SUN4E_ARCH 0x60 /* arch value for Sun 4e */
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#define SUN4E_MACH_120 0x01
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#define CPU_SUN4E (SUN4E_ARCH + CPU_MACH)
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#define CPU_SUN4E_120 (SUN4E_ARCH + SUN4E_MACH_120)
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/*
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* early sun4m architectures
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*/
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#define SUN4M_ARCH 0x70 /* arch value for Sun 4m */
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#define SUN4M_MACH_60 0x01
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#define SUN4M_MACH_50 0x02
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#define SUN4M_MACH_40 0x03
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#define CPU_SUN4M_60 (SUN4M_ARCH + SUN4M_MACH_60)
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#define CPU_SUN4M_50 (SUN4M_ARCH + SUN4M_MACH_50)
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#define CPU_SUN4M_40 (SUN4M_ARCH + SUN4M_MACH_40)
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#define CPU_SUN4M (SUN4M_ARCH + CPU_MACH)
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/*
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* The ultimate value of 'cputype'. If you find the top bit
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* set, then it means - "go look at the properties in the device tree"
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*
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* In this case, nothing else can or should be inferred from the value
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* of 'cputype' - the other bits are free for whatever e.g. manufacturing
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* wants to do with them.
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*/
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#define OBP_ARCH 0x80 /* arch value for 4m, 4d and later */
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/*
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* Global kernel variables of interest
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*/
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#if defined(_KERNEL) && !defined(_ASM)
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extern short cputype; /* machine type we are running on */
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extern int dvmasize; /* usable dvma size in clicks */
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/*
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* Cache defines - right now these are only used on sun4m machines
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*
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* Each bit represents an attribute of the system's caches that
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* the OS must handle. For example, VAC caches must have virtual
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* alias detection, VTAG caches must be flushed on every demap, etc.
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*/
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#define CACHE_NONE 0 /* No caches of any type */
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#define CACHE_VAC 0x01 /* Virtual addressed cache */
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#define CACHE_VTAG 0x02 /* Virtual tagged cache */
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#define CACHE_PAC 0x04 /* Physical addressed cache */
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#define CACHE_PTAG 0x08 /* Physical tagged cache */
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#define CACHE_WRITEBACK 0x10 /* Writeback cache */
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#define CACHE_IOCOHERENT 0x20 /* I/O coherent cache */
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extern int cache;
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/*
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* Virtual Address Cache defines- right now just determine whether it
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* is a writeback or a writethru cache.
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*
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* MJ: a future merge with some of the sun4m structure defines could
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* MJ: tell us whether or not this cache has I/O going thru it, or
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* MJ: whether it is consistent, etc.
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*/
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#define NO_VAC 0x0
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#define VAC_WRITEBACK 0x1 /* this vac is a writeback vac */
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#define VAC_WRITETHRU 0x2 /* this vac is a writethru vac */
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#define VAC_IOCOHERENT 0x100 /* i/o uses vac consistently */
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/* set this to zero if no vac */
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extern int vac;
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#ifdef IOC
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extern int ioc; /* there is an I/O cache */
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#else
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#define ioc 0
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#endif /* IOC */
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#ifdef BCOPY_BUF
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extern int bcopy_buf; /* there is a bcopy buffer */
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#else
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#define bcopy_buf 0
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#endif /* BCOPY_BUF */
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#endif /* defined(_KERNEL) && !defined(_ASM) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SYS_CPU_H */
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