211 lines
8.9 KiB
C
Executable File
211 lines
8.9 KiB
C
Executable File
/*
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* Copyright (c) 1992 by Sun Microsystems, Inc.
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*/
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#ifndef _SYS_BMAC_H
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#define _SYS_BMAC_H
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#pragma ident "@(#)bmac.h 1.16 94/06/15 SMI"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Declarations and definitions specific to the BigMAC chip.
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*
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* The BigMAC chip will provide the MAC functons for 10 or 100 Mbps CSMA/CD
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* protocol based interface. The QEC will control the transfer of data
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* between the host memory, buffer memory and the BigMAC. When transmitting
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* a frame will be moved from the Sbus to buffer memory. When an entire
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* frame is present in the buffer memory, the QEC will move the data from
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* the buffer memory to BigMAC. Same is the case while receiving. When the
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* entire frame is present in the buffer memory, QEC will move frame from
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* buffer memory to host's memory.
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*
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*/
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/*
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* BigMAC Register Set.
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* BigMAC addresses map on a SBus word boundry. So all registers are
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* declared for a size of 32 bits. Registers that use fewer than 32
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* bits will return 0 in the bits not used.
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* XXX Do spaces between registers need to be paded.
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*/
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struct bmac {
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u_int xifc; /* XIF Configuration register [3-0] (RW) */
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u_char pad2[252]; /* XXX h/w team to confirm */
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u_int stat; /* status register [15-0] (R-auto clear) */
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u_int mask; /* interrupt mask register [15-0] (RW) */
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u_char pad3[256];
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u_int txrst; /* tx software reset (RW) */
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u_int txcfg; /* tx configuration register [9-0] (RW) */
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u_int ipg1; /* Inter Packet Gap 1 [7-0] (RW) */
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u_int ipg2; /* Inter Packet Gap 2 [7-0] (RW) */
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u_int alimit; /* attempt limit register [7-0] (RW) */
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u_int slot; /* slot time register [7-0] (RW) */
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u_int palen; /* preamble length register [7-0] (RW) */
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u_int papat; /* preamble pattern register [7-0] (RW) */
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u_int txsfd; /* tx start frame delimiter [7-0] (RW) */
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u_int jam; /* jam size register [7-0] (RW) */
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u_int txmax; /* tx maximum packet size [12-0] (RW) */
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u_int txmin; /* tx minimum frame size [7-0] (RW) */
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u_int parg; /* peak attempt count [7-0] (RW) */
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u_int dcnt; /* defer timer counter [15-0] (RW) */
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u_int nccnt; /* normal collision counter [15-0] (RW) */
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u_int ntcnt; /* network collision counter [15-0] (RW) */
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u_int excnt; /* excess collision counter [7-0] (RW) */
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u_int ltcnt; /* late collision counter [7-0] (RW) */
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u_int rseed; /* random number seed [9-0] (RW) */
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u_int txsm; /* tx state machine register [8-0] (R) */
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u_char pad4[176];
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u_int rxrst; /* rx software reset register (RW) */
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u_int rxcfg; /* rx configuration register [11-0] (RW) */
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u_int rxmax; /* rx maximum packet size [12-0] (RW) */
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u_int rxmin; /* rx minimum frame size [7-0] (RW) */
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u_int madd2; /* mac address register 2 [47-32] (RW) */
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u_int madd1; /* mac address register 1 [31-16] (RW) */
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u_int madd0; /* mac address register 0 [15-0] (RW) */
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u_int frcnt; /* receive frame count [15-0] (RW) */
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u_int lecnt; /* rx giant length error count [7-0] (RW) */
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u_int aecnt; /* rx alignment error count [7-0] (RW) */
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u_int fecnt; /* receive crc error count [7-0] (RW) */
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u_int rxsm; /* rx state machine register (R) */
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u_int rxcv; /* rx code voilation register (R) */
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u_char pad5[4];
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u_int hash3; /* hash table 3 [63-48] (RW) */
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u_int hash2; /* hash table 2 [47-32] (RW) */
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u_int hash1; /* hash table 1 [31-16] (RW) */
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u_int hash0; /* hash table 0 [15-0] (RW) */
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u_int afr2; /* addr filter register 0_2 [15-0] (RW) */
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u_int afr1; /* addr filter register 0_1 [15-0] (RW) */
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u_int afr0; /* addr filter register 0_0 [15-0] (RW) */
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u_int afmr; /* addr filter mask reg 0 [15-0] (RW) */
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};
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/*
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* BigMAC Register Bit Masks.
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* XXX add right-shift values later.
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*/
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#define BMAC_XIFC_MODE_SERIAL (0x08) /* Mode strapp(1==serial, 0==nibble */
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#define BMAC_XIFC_LPBK (0x04) /* Enable Loopback mode */
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#define BMAC_XIFC_RSVD (0x02) /* reserved, should be written as 1 */
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#define BMAC_XIFC_ENAB (0x01) /* Enable output drivers */
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#define BMAC_STAT_DEFER (0x8000) /* Defer Timer */
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#define BMAC_STAT_NETCOLL (0x4000) /* network collision */
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#define BMAC_STAT_LCOL (0x2000) /* late collision */
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#define BMAC_STAT_EXCCOLL (0x1000) /* excessive collision */
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#define BMAC_STAT_NORCOLL (0x0800) /* normal collision */
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#define BMAC_STAT_MAXPKT (0x0400) /* giant pkt err */
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#define BMAC_STAT_UFLO (0x0200) /* tx fifo underflow */
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#define BMAC_STAT_TXINTR (0x0100) /* tx interrupt */
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#define BMAC_STAT_RXCV (0x0040) /* rx code voilation */
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#define BMAC_STAT_OFLO (0x0020) /* rx fifo overflow */
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#define BMAC_STAT_LENGTH (0x0010) /* rx length error */
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#define BMAC_STAT_CRC (0x0008) /* crc error */
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#define BMAC_STAT_ALNERR (0x0004) /* alignment error */
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#define BMAC_STAT_RXFRMC (0x0002) /* rx frame counter */
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#define BMAC_STAT_RXINTR (0x0001) /* rx interrupt */
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#define BMAC_MASK_DEFERM (0x8000) /* Defer Timer Mask */
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#define BMAC_MASK_NETCOLLM (0x4000) /* network collision mask */
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#define BMAC_MASK_LCOLM (0x2000) /* late collision mask */
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#define BMAC_MASK_EXCCOLLM (0x1000) /* excessive collision mask */
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#define BMAC_MASK_NORCOLLM (0x0800) /* normal collision mask */
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#define BMAC_MASK_MAXPKTM (0x0400) /* max packet size mask */
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#define BMAC_MASK_UFLOM (0x0200) /* tx fifo underflow mask */
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#define BMAC_MASK_TXINTRM (0x0100) /* tx interrupt mask */
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#define BMAC_MASK_RXCV (0x0040) /* rx code voilation mask */
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#define BMAC_MASK_OFLOM (0x0020) /* rx fifo overflow mask */
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#define BMAC_MASK_LENGTH (0x0010) /* rx length error mask */
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#define BMAC_MASK_CRCM (0x0008) /* crc error mask */
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#define BMAC_MASK_ALNERRM (0x0004) /* alignment error mask */
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#define BMAC_MASK_RXFRMCM (0x0002) /* rx frame counter mask */
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#define BMAC_MASK_RXINTRM (0x0001) /* rx interrupt mask */
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#define BMAC_MASK_OTHER (0x7e7e) /* other than TINT RINT DEFER */
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#define BMAC_MASK_TINT_RINT (0x0101) /* TINT and RINT */
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#define BMAC_TXCFG_FDUP (0x0200) /* Full Duplex */
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#define BMAC_TXCFG_NGU (0x0100) /* Never Give Up/No Backoff */
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#define BMAC_TXCFG_NFCS (0x0080) /* no FCS will be generated */
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#define BMAC_TXCFG_IGCOLL (0x0040) /* tx ignore collision */
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#define BMAC_TXCFG_SLOW (0x0020) /* carrier detect before tx */
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#define BMAC_TXCFG_FIFO (0x0010) /* default tx fifo threshold */
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#define BMAC_TXCFG_ENAB (0x0001) /* tx enable */
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#define BMAC_RXCFG_ADDR (0x1000) /* rx enable address filter */
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#define BMAC_RXCFG_HASH (0x0800) /* rx enable hash filter */
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#define BMAC_RXCFG_GRPROM (0x0400) /* rx promiscuous group mode */
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#define BMAC_RXCFG_MYOWN (0x0200) /* rx filter own packets */
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#define BMAC_RXCFG_CRC (0x0100) /* rx disable CRC stripping */
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#define BMAC_RXCFG_ERR (0x0080) /* rx disable error checking */
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#define BMAC_RXCFG_PROMIS (0x0040) /* rx enable promiscous */
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#define BMAC_RXCFG_STRIP (0x0020) /* rx strip pad bytes */
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#define BMAC_RXCFG_FIFO (0x000e) /* default rx fifo threshold */
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#define BMAC_RXCFG_ENAB (0x0001) /* rx enable */
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#define BMACTXRSTDELAY (125) /* 125 us wait period */
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#define BMACRXRSTDELAY (40) /* 3.2 us wait period */
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struct bmactcvr {
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u_int pal1; /* trasnceiver pal */
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u_int pal2; /* management pal */
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};
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#define BMACLNKTIME (500000) /* Length of time pulses send */
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/* P1 Board */
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#define BMAC_TPAL1_XM_SERIAL (1 << 0) /* XIF mode 0=nibble 1=serial */
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#define BMAC_TPAL1_LB (1 << 1) /* External loopback */
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#define BMAC_TPAL1_MS (1 << 2) /* Media Sense */
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#define BMAC_TPAL1_LINKTESTEN (1 << 3) /* Link Test Enable */
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#define BMAC_TPAL1_LINKSTATUS (1 << 4) /* Link Test Status */
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/* P1.5 Board */
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#define BMAC_TPAL1_PGYBAC_DIS (1 << 0) /* XIF mode 0=nibble 1=serial */
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#define BMAC_TPAL1_LOOP_EN (1 << 1) /* External loopback */
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#define BMAC_TPAL1_CLK_LOOP_EN (1 << 2) /* Media Sense */
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#define BMAC_TPAL1_CLK_FSTSLW (1 << 3) /* Link Test Enable */
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#define BMAC_TPAL2_MDC_BIT_POS 0 /* Mgmt. data clock */
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#define BMAC_TPAL2_MDIO_EN_BIT_POS 1 /* Mgmt. data output enable */
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#define BMAC_TPAL2_MII_MDIO_BIT_POS 2 /* Management data */
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#define BMAC_TPAL2_PGYBAC_MDIO_BIT_POS 3 /* Tx enable timeout error */
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#define BMAC_TPAL2_MDC (1 << BMAC_TPAL2_MDC_BIT_POS)
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#define BMAC_TPAL2_MDIO_EN (1 << BMAC_TPAL2_MDIO_EN_BIT_POS)
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#define BMAC_TPAL2_MII_MDIO (1 << BMAC_TPAL2_MII_MDIO_BIT_POS)
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#define BMAC_TPAL2_PGYBAC_MDIO (1 << BMAC_TPAL2_PGYBAC_MDIO_BIT_POS)
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/*
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* Management Frame Structure:
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* <IDLE> <ST><OP><PHYAD><REGAD><TA> <DATA> <IDLE>
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* READ: <01><10><AAAAA><RRRRR><Z0><DDDDDDDDDDDDDDDD>
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* WRITE: <01><01><AAAAA><RRRRR><10><DDDDDDDDDDDDDDDD>
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*/
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#define BMAC_EXTERNAL_PHYAD 0x0
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#define BMAC_INTERNAL_PHYAD 0x1
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#define BMAC_MII_CTLREG 0x0
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#define BMAC_MII_STATREG 0x1
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/* Control Register Bit Definitions */
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#define BMAC_MII_CTL_RESET (1 << 15) /* PHY Reset */
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#define BMAC_MII_CTL_LOOPBACK (1 << 14) /* Loopback Mode */
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#define BMAC_MII_CTL_SPEED_100 (1 << 13) /* 1=100Mbps; 0=10Mbps */
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#define BMAC_MII_CTL_AUTO_SPEED (1 << 12)
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#define BMAC_MII_CTL_POWER_DOWN (1 << 11)
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#define BMAC_MII_CTL_ISOLATE (1 << 10) /* Isolate PHY from MII */
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/* Status Register Bit Definitions */
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#define BMAC_MII_STAT_LINKUP (1 << 2)
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#define BMAC_MII_STAT_JABBER (1 << 1)
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#define BMAC_MII_STAT_EXT_CAP (1 << 0)
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SYS_BMAC_H */
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