191 lines
6.7 KiB
C
Executable File
191 lines
6.7 KiB
C
Executable File
/*
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* Copyright (c) 1990 by Sun Microsystems, Inc.
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*/
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#ifndef _SYS_LANCE_H
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#define _SYS_LANCE_H
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#pragma ident "@(#)lance.h 1.6 93/05/27 SMI"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Declarations and definitions specific to the Am7990
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* LANCE Ethernet Local Area Network Controller.
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*
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* Header file dependencies:
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* sys/types.h
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*/
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/*
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* The LANCE chip saves address pins by accessing
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* several registers with one address pin by first writing the
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* register address to an internal address register, then reading
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* or writing a data register. To use this safely, care must be
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* taken that the driver isn't reentered between the writing
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* of the address register and the access to the data register,
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* lest the reentered code try to touch the registers and
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* screw up the sequence.
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*
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* There are 4 registers accessible with this scheme, CSR0, CSR1,
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* CSR2, and CSR3. In normal operation, only CSR0 can be or
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* needs to be accessed, so the driver normally leaves a 0 in the
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* Register Address Port, allowing CSR0 to be accessed simply by
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* accessing the Register Data Port. During the initialization
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* sequence, when the other CSRs need to be accessed, the appropriate
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* CSR address is written into the address port, and afterwards
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* the 0 is put back in the address port.
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*/
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struct lanceregs {
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volatile u_short lance_rdp; /* Register Data Port */
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/*
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* Strictly speaking, the following definition is
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*
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* u_short : 14,
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* rap : 2;
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*
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* but compilers will often generate byte accesses on
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* machines where the lance chip needs to be accessed
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* as a halfword (e.g., 4/60,3/80), so we'll declare
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* it as a plain halfword here.
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*
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*/
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volatile u_short lance_rap; /* Register Address Port */
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};
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#define lance_csr lance_rdp
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#define LANCE_CSR0 0
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#define LANCE_CSR1 1
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#define LANCE_CSR2 2
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#define LANCE_CSR3 3
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/*
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* Control and status bits for CSR0.
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* These behave somewhat strangely, but the net effect is that
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* bit masks may be written to the register which affect only
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* those functions for which there is a one bit in the mask.
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* The exception is the interrupt enable, which must be explicitly
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* set to the correct value in each mask that is used.
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*
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* RO - Read Only, writing has no effect
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* RC - Read, Clear. Writing 1 clears, writing 0 has no effect
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* RW - Read, Write.
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* W1 - Write with 1 only. Writing 1 sets, writing 0 has no effect.
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* Reading gives unpredictable data but doesn't hurt anything.
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* RW1 - Read, Write with 1 only. Writing 1 sets, writing 0 has no effect.
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*/
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#define LANCE_ERR 0x8000 /* RO BABL | CERR | MISS | MERR */
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#define LANCE_BABL 0x4000 /* RC transmitted too many bits */
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#define LANCE_CERR 0x2000 /* RC No Heartbeat */
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#define LANCE_MISS 0x1000 /* RC Missed an incoming packet */
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#define LANCE_MERR 0x0800 /* RC Memory Error; no acknowledge */
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#define LANCE_RINT 0x0400 /* RC Received packet Interrupt */
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#define LANCE_TINT 0x0200 /* RC Transmitted packet Interrupt */
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#define LANCE_IDON 0x0100 /* RC Initialization Done */
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#define LANCE_INTR 0x0080 /* RO BABL|MISS|MERR|RINT|TINT|IDON */
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#define LANCE_INEA 0x0040 /* RW Interrupt Enable */
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#define LANCE_RXON 0x0020 /* RO Receiver On */
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#define LANCE_TXON 0x0010 /* RO Transmitter On */
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#define LANCE_TDMD 0x0008 /* W1 Transmit Demand (send it now) */
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#define LANCE_STOP 0x0004 /* RW1 Stop */
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#define LANCE_STRT 0x0002 /* RW1 Start */
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#define LANCE_INIT 0x0001 /* RW1 Initialize */
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/*
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* CSR1 is the low 16 bits of the address of the initialization block
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* CSR2 is the high 8 bits of the address of the initialization block
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* the high 8 bits of the register must be 0
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* CSR3 mode bits:
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*/
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#define LANCE_BSWP 0x4 /* Byte Swap (on for 68000 byte order) */
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#define LANCE_ACON 0x2 /* ALE Control (on for active low ALE) */
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#define LANCE_BCON 0x1 /* Byte Control (see the manual) */
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/* The address contained in this structure must be longword aligned */
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struct lancering { /* Descriptor Ring Pointer */
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u_short lr_laddr; /* Low 16 bits of ring address */
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u_char lr_len : 3; /* Binary exponent of no. of ring entries */
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u_char : 5; /* Reserved */
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u_char lr_haddr; /* High 16 bits of ring address */
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};
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/*
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* Initialization Block. This structure is constructed in memory,
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* and it's address is written into the chip during initialization.
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* The chip then fetches it's initialization info from the structure.
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*/
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struct lance_init_block {
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/* In the normal mode, these 16 bits are all 0 */
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u_short ib_prom : 1; /* Promiscuous Mode */
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u_short : 8; /* Reserved */
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u_short ib_intl : 1; /* Internal Loopback */
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u_short ib_drty : 1; /* Disable Retry */
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u_short ib_coll : 1; /* Force Collision */
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u_short ib_dtcr : 1; /* Disable Transmit CRC */
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u_short ib_loop : 1; /* Loopback */
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u_short ib_dtx : 1; /* Disable Transmitter */
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u_short ib_drx : 1; /* Disable Receiver */
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/*
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* The bytes must be swapped within the word, so that, for example,
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* the address: 8:0:20:1:25:5a is written in the order
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* 0 8 1 20 5a 25
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*/
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u_char ib_padr[6];
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u_short ib_ladrf[4]; /* Multicast logical address filter */
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struct lancering ib_rdrp; /* Receive Descriptor Ring Pointer */
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struct lancering ib_tdrp; /* Transmit Descriptor Ring Pointer */
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};
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struct lmd { /* Message Descriptor */
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u_short lmd_ladr; /* Low Order 16 Address Bits */
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u_char lmd_flags;
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u_char lmd_hadr: 8; /* High Order 8 Address Bits */
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u_short lmd_bcnt; /* Buffer Byte Count (maximum length) */
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u_short lmd_mcnt; /* Message Byte Count (actual length) */
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};
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#define lmd_flags3 lmd_mcnt /* for Transmit message descriptor */
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/* Bits common to both rmds and tmds */
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#define LMD_OWN 0x80 /* Chip owns the descriptor */
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#define LMD_ERR 0x40 /* Error occurred */
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#define LMD_STP 0x02 /* Start of Packet */
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#define LMD_ENP 0x01 /* End of Packet */
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/* Bits in rmd flags */
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#define RMD_FRAM 0x20 /* Framing error */
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#define RMD_OFLO 0x10 /* Internal Silo Overflowed. Valid if !ENP */
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#define RMD_CRC 0x08 /* CRC Error */
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#define RMD_BUFF 0x04 /* Didn't have a buffer for the packet */
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/* bits in tmd flags */
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#define TMD_RES 0x20 /* Reserved, lance writes this with a zero */
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#define TMD_MORE 0x10 /* More than one retry was needed */
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#define TMD_ONE 0x08 /* Exactly One Retry, valid only if !LCOL */
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#define TMD_DEF 0x04 /* Deferred (net was initially busy) */
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/* Bits for lmd_errflags */
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#define TMD_BUFF 0x8000 /* Buffer Error (imples underflow too) */
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#define TMD_UFLO 0x4000 /* Underflow Error */
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#define TMD_LCOL 0x1000 /* Late Collision */
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#define TMD_LCAR 0x0800 /* Loss of Carrier */
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#define TMD_RTRY 0x0400 /* More than 16 Retry's */
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#define TMD_TDR 0x003f /* Time Domain Reflectometry counter mask */
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/* Handy combo errflags */
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#define TMD_ANYERROR (TMD_BUFF|TMD_UFLO|TMD_LCOL|TMD_LCAR|TMD_RTRY)
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#define LANCEALIGN (8)
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#define LANCEALIGNMASK (0x3);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SYS_LANCE_H */
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