126 lines
4.2 KiB
C
Executable File
126 lines
4.2 KiB
C
Executable File
/*
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* Copyright (c) 1985-1991, by Sun Microsystems, Inc.
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*/
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#ifndef _SYS_MEMERR_H
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#define _SYS_MEMERR_H
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#pragma ident "@(#)memerr.h 1.11 93/05/26 SMI"
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/* From SunOS 4.1.1 sun4/memerr.h 1.6 */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* All Sun-4 implementations have either memory parity error detection
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* or memory equipped with error correction (ECC). The memory error
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* register consists of a control and an address register. If an error
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* occurs, the control register stores information relevant to the error.
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* The memory address error register stores the virtual address, the
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* context number, and the CPU/DVMA bit of the memory cycle at which
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* the error was detected. Errors are reported via a non-maskable
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* level 15 interrupt. In case of multiple (stacked) memory errors,
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* the information relation to the first error is latched in the
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* memory error register. The interrupt is held pending and the error
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* information in the memory error register is latched (frozen) until
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* it is cleared (unfrozen) by a write to bits <31..24> of the memory
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* error address register.
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*/
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#define OBIO_MEMERR_ADDR 0xF4000000 /* address of memerr in obio space */
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#define MEMERR_ADDR (MDEVBASE + 0x6000) /* virtual address mapped to */
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#ifdef _ASM
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#define MEMERR MEMERR_ADDR /* virtual address we map memerr to be at */
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#else /* _ASM */
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#if defined(_KERNEL)
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struct regs; /* foward declaration, keeps lint happy */
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#include <sys/pte.h>
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struct memerr {
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u_int me_err; /* memory error register */
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#define me_per me_err /* parity error register */
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#define me_eer me_err /* ECC error register */
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u_int me_vaddr; /* virtual address of error */
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};
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#define MEMERR ((struct memerr *)(MEMERR_ADDR))
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void memerr_init(void);
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void memerr_signal(caddr_t);
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void memerr_330(u_int, u_int, caddr_t, unsigned, struct regs *);
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int parerr_reset(caddr_t, struct pte *);
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#endif /* defined(_KERNEL) */
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#endif /* _ASM */
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/*
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* Bits for the memory error register when used as parity error register
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*/
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#define PER_CTX 0x1fe00 /* r/o - context number mask */
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#define PER_DVMA 0x100 /* r/o - DVMA access indicator */
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#define PER_INTR 0x80 /* r/o - 1 = parity interrupt pending */
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#define PER_INTENA 0x40 /* r/w - 1 = enable interrupt on parity error */
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#define PER_TEST 0x20 /* r/w - 1 = write inverse parity */
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#define PER_CHECK 0x10 /* r/w - 1 = enable parity checking */
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#define PER_ERR24 0x08 /* r/o - 1 = parity error <24..31> */
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#define PER_ERR16 0x04 /* r/o - 1 = parity error <16..23> */
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#define PER_ERR08 0x02 /* r/o - 1 = parity error <8..15> */
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#define PER_ERR00 0x01 /* r/o - 1 = parity error <0..7> */
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#define PER_ERR 0x0F /* r/o - mask for some parity error occuring */
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#define PARERR_BITS \
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"\20\11DVMA\10INTR\7INTENA\6TEST\5CHECK\4ERR24\3ERR16\2ERR08\1ERR00"
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#define PER_DVMA_SHIFT 8
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#define PER_CTX_SHIFT 9
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/*
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* Bits for the memory error register when used as ECC error register
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*/
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#define EER_CTX 0x1fe00 /* r/o - context number mask */
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#define EER_DVMA 0x100 /* r/o - DVMA access indicator */
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#define EER_INTR 0x80 /* r/o - ECC memory interrupt pending */
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#define EER_INTENA 0x40 /* r/w - enable interrupts on errors */
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#define EER_BUSHOLD 0x20 /* r/w - hold memory bus mastership */
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#define EER_CE_ENA 0x10 /* r/w - enable CE recording */
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#define EER_TIMEOUT 0x08 /* r/o - Sirius bus time out */
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#define EER_WBACKERR 0x04 /* r/o - write back error */
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#define EER_UE 0x02 /* r/o - UE, uncorrectable error */
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#define EER_CE 0x01 /* r/o - CE, correctable (single bit) error */
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#define EER_ERR 0x0F /* r/o - mask for some ECC error occuring */
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#define ECCERR_BITS \
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"\20\11DVMA\10INTR\7INTENA\6BUSHOLD\5CE_ENA\4TIMEOUT\3WBACKERR\2UE\1CE"
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#define EER_DVMA_SHIFT 8 /* shift for DVMA bit */
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#define EER_CTX_SHIFT 9 /* shift for context number */
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#define ER_INTR 0x80 /* mask for ECC/parity interrupt pending */
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#define ER_INTENA 0x40 /* mask for ECC/parity enable interrupt */
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#define MEMINTVL 60 /* sixty second delay for softecc */
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/*
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* stingray parity error SIMM ID print defines
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*/
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#define CONF 0xE
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#define CONF_POS 1
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#define SIMMADDR 0x0FC00000
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#define SIMMADDR_POS 22
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/*
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* Flags to define type of memory error.
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*/
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#define MERR_SYNC 0x0
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#define MERR_ASYNC 0x1
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SYS_MEMERR_H */
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