274 lines
7.5 KiB
C
Executable File
274 lines
7.5 KiB
C
Executable File
/*
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* Copyright (c) 1990 by Sun Microsystems, Inc.
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*/
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/*
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* sun4d physical address defines
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*/
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#ifndef _SYS_PHYSADDR_H
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#define _SYS_PHYSADDR_H
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#pragma ident "@(#)physaddr.h 1.26 95/10/19 SMI"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* sun4d systems have 36 bit physical addresses.
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* The kernel generally represents them with u_longlong's.
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* However, fixed I/O space addresses are often accessed via
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* ASI 0x2* for paddr[35:32] with a u_int for paddr[31:0].
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*/
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/*
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* I/O space addresses have paddr[35] = 1;
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*/
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#define PA_IS_IO_SPACE(pa) ((pa) & ((u_longlong_t)1 << 35))
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/*
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* CPU Unit's device_id can be quickly derived from cpu_id
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*/
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#define PROP_DEVICE_ID "device-id"
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#ifdef sun4d
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#define CPUID_2_DEVID(cpu_id) ((cpu_id) << 3)
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#else /* cray4d */
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#define CPUID_ABCD_MASK 0x3
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#define CPUID_SLOT_MASK 0x3c
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#define CPUID_2_DEVID(cpu_id) ((cpu_id) & CPUID_ABCD_MASK) << 5) | \
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((cpu_id) & CPUID_SLOT_MASK) >> 1)
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#endif
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/*
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* Control Status and Register (CSR) Space
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* for functional units replicated per XDBUS
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*/
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#define ASI_CSR 0x2f
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#define CSR_ADDR_BASE 0xE0000000 /* paddr[35:28] = 0xFE */
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#define CSR_DEVID_SHIFT 20 /* paddr[27:20] = devid[7:0] */
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#define CSR_BUS_SHIFT 8 /* paddr[9:8] = XDBUS index */
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/*
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* Extended Control Status and Register (ECSR) Space
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* for functional units not replicated per XDBUS
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*/
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#define ASI_ECSR 0x2f
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#define ECSR_ADDR_BASE 0x00000000 /* paddr[35:32] = 0xF */
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#define ECSR_DEVID_SHIFT 24 /* paddr[31:25] = devid[7:1] */
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/* devid[0] is 0 in ECSR space */
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/* consolidate this stuff */
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#define CSR_WIDTH 4
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#define DEV_ID_WIDTH 8
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#define CPU_INDEX_WIDTH 5 /* status3 slot + A/B encoding */
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#define CSR_CPU_PREFIX (0xe << CPU_INDEX_WIDTH)
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#define CPU_2_CSR_SHIFT ((32 - CSR_WIDTH) - CPU_INDEX_WIDTH)
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#define CPU_2_ECSR_SHIFT (32 - CPU_INDEX_WIDTH)
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#define DEV_2_ECSR_SHIFT (32 - DEV_ID_WIDTH)
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#if !defined(_ASM)
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/*
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* prototypes for physical address ASI inlines in sun4d.il.cpp
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*/
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extern u_char lduba_2f(u_char *addr);
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extern u_short lduha_2f(u_short *addr);
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extern u_int lda_2f(u_int *addr);
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extern u_longlong_t ldda_2f(u_longlong_t *src);
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extern void stba_2f(u_char value, u_char *addr);
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extern void stha_2f(u_short value, u_short *addr);
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extern void sta_2f(u_int value, u_int *addr);
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extern void stda_2f(u_longlong_t value, u_longlong_t *addr);
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extern u_int swapa_2f(u_int value, u_int offset);
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extern u_longlong_t ldda_02(u_longlong_t *src);
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extern void sta_28(u_int value, u_int *addr);
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extern void sta_29(u_int value, u_int *addr);
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extern void sta_2a(u_int value, u_int *addr);
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extern void sta_2b(u_int value, u_int *addr);
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#endif _ASM
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/*
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* Decode SBus Space physical addresses.
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* Valid for all sun4d variants, -- system board numbers are [0 - 15].
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*/
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#define PA_SBUS_SPACE_BASE ((u_longlong_t)0x800000000)
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#define PA_SBUS_SPACE_MASK ((u_longlong_t)0xc00000000)
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#define PA_SBUS_SYSBRD_SHIFT 30
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#define PA_SBUS_SYSBRD_MASK ((u_longlong_t)0xF << PA_SBUS_SYSBRD_SHIFT)
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#define PA_SBUS_TO_SYSBRD(pa) \
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((u_int)(((pa) & PA_SBUS_SYSBRD_MASK) >> PA_SBUS_SYSBRD_SHIFT))
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#define PA_SBUS_SLOT_SHIFT 28
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#define PA_SBUS_SLOT_MASK (0x3 << PA_SBUS_SLOT_SHIFT)
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#define PA_SBUS_TO_SBUS_SLOT(pa) \
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(((u_int)(pa) & PA_SBUS_SLOT_MASK) >> PA_SBUS_SLOT_SHIFT)
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#define PA_SBUS_OFFSET_MASK 0x0FFFFFFF
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#define PA_SBUS_TO_SBUS_OFF(pa) \
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((u_int)(pa) & PA_SBUS_OFFSET_MASK)
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/*
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* Cache Controller registers
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*/
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#define OFF_CC_REGS 0x01f00000
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#define OFF_CC_STREAM_DATA 0x0
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#define OFF_CC_STREAM_DATA_SIZE 0x3f
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#define OFF_CC_STREAM_SRC_ADDR 0x100
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#define OFF_CC_STREAM_DEST_ADDR 0x200
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#define OFF_CC_REF_COUNT 0x300
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#define OFF_CC_INTR_PENDING 0x406
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#define OFF_CC_INTR_MASK 0x506
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#define OFF_CC_INTR_PENDING_CLEAR 0x606
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#define OFF_CC_INTR_GEN_ASI2 0x704 /* ASI 0x2 access only */
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#define OFF_CC_BIST 0x804 /* ASI 0x2 access only */
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#define OFF_CC_CONTROL 0xa04
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#define OFF_CC_STATUS 0xb00
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#define OFF_CC_RESET 0xc04
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#define OFF_CC_ERROR 0xe00
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#define OFF_CC_COMPONENT_ID 0xf04
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#define MXCC_CID_MREV_MASK 0xF0
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#define MXCC_CID_MREV_SHIFT 4
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#define MXCC_CID_MREV_1 0
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#define MXCC_CID_MREV_2 4
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#define MXCC_CID_MREV_3 8
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#define MXCC_CID_MREV_4 12
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#if !defined(_ASM)
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#define MXCC_MC_OK(mrev) \
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((mrev) >= MXCC_CID_MREV_4)
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#define mxcc_cid_get_ecsr(cpuid) \
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lda_2f((u_int *)(ECSR_ADDR_BASE + \
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(CPUID_2_DEVID(cpuid) << ECSR_DEVID_SHIFT) + \
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OFF_CC_REGS + OFF_CC_COMPONENT_ID))
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#define intr_clear_pend_ecsr(id, level) \
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stha_2f(1 << (level), \
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(u_short *)(OFF_CC_REGS | OFF_CC_INTR_PENDING_CLEAR | \
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((id) << CPU_2_ECSR_SHIFT)))
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#define nvram_get_byte(id, off) \
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lduba_2f((u_char *)(((id) << CPU_2_ECSR_SHIFT) | (off) | OFF_BB_NVRAM))
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#define nvram_set_byte(id, off, val) \
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stba_2f((val), \
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(u_char *)(((id) << CPU_2_ECSR_SHIFT) | (off) | OFF_BB_NVRAM))
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#define bb_ecsr_read_stat2(id) \
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lduba_2f((u_char *) ((CPUID_2_DEVID(id) << ECSR_DEVID_SHIFT) | \
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XOFF_FASTBUS_STATUS2))
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#endif _ASM
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/*
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* Bus Watcher registers
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*/
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#define OFFSET_TIMER_LIMIT 0x0
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#define OFFSET_TIMER_COUNTER 0x4
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#define OFFSET_TIMER_NONDEST_LIMIT 0x8
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#define OFFSET_TIMER_CONTROL 0xc
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#define OFFSET_USER_TIMER_MSW OFFSET_TIMER_LIMIT
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#define OFFSET_USER_TIMER_LSW OFFSET_TIMER_COUNTER
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#define OFF_BW_COMPOENT_ID 0
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#define OFF_BW_DBUS_CTL_STAT 0x8
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#define OFF_BW_DBUS_DATA 0x10
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#define OFF_BW_CONTROL 0x1000
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#define OFF_BW_INTR_TABLE 0x1040
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#define OFF_BW_INTR_TABLE_CLEAR 0x1080
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#define OFF_BW_PRESCALER 0x10c0
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#define OFF_BW_PROFILE_TIMER 0x2000
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#define OFF_BW_TICK_TIMER 0x3000
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#define OFF_BW_PROFILE_TIMER_LIMIT \
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(OFF_BW_PROFILE_TIMER | OFFSET_TIMER_LIMIT)
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#define OFF_BW_PROFILE_TIMER_COUNTER \
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(OFF_BW_PROFILE_TIMER | OFFSET_TIMER_COUNTER)
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#define OFF_BW_PROFILE_TIMER_NONDEST_LIMIT \
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(OFF_BW_PROFILE_TIMER | OFFSET_TIMER_NONDEST_LIMIT)
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#define OFF_BW_PROFILE_TIMER_CONTROL \
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(OFF_BW_PROFILE_TIMER | OFFSET_TIMER_CONTROL)
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#define OFF_BW_TICK_TIMER_LIMIT \
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(OFF_BW_TICK_TIMER | OFFSET_TIMER_LIMIT)
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#define OFF_BW_TICK_TIMER_COUNTER \
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(OFF_BW_TICK_TIMER | OFFSET_TIMER_COUNTER)
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#define OFF_BW_TICK_TIMER_NONDEST_LIMIT \
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(OFF_BW_TICK_TIMER | OFFSET_TIMER_NONDEST_LIMIT)
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#define BW_LCCNT_WRITE_UPDATE 0
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#define BW_LCCNT_WRITE_INVALIDATE 63
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#define BW_CTL_LCCNT_SHIFT 6
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#define BW_CTL_LCCNT_MASK ((0x3f) << BW_CTL_LCCNT_SHIFT)
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#define bw_cntl_get(a) lda_2f((u_int *)((a) | OFF_BW_CONTROL))
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#define bw_cntl_set(v, a) sta_2f((u_int) (v), (u_int *) ((a) | OFF_BW_CONTROL))
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/*
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* Boot Bus
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*/
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#define OFF_BB_NVRAM 0x280000
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#define OFF_BB_NVRAM_CHECKSUM 0x0 /* OBP dependency */
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#define XOFF_FASTBUS_STATUS2 0x120000
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/*
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* IOC registers
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*/
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#define OFF_IOC_COMPONENT_ID 0x0
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#define OFF_IOC_DBUS_CONTROL_STATUS 0x8
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#define OFF_IOC_DBUS_DATA 0x10
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#define OFF_IOC_CONTROL 0x1000
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#define IOC_CID_DW_BUG 0x10ADD07D
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#define IOC_CID_NEW 0x20ADD07D
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#define ioc_get_cid(devid, bus) \
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lda_2f((u_int *)(CSR_ADDR_BASE + ((devid) << CSR_DEVID_SHIFT) + \
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((bus) << CSR_BUS_SHIFT) + OFF_IOC_COMPONENT_ID))
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/*
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* SBI registers
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*/
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#define OFF_SBI_COMPONENT_ID 0x0
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#define OFF_SBI_CONTROL 0x4
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#define OFF_SBI_STATUS 0x8
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#define OFF_SBI_SLOT0_CONFIG 0x10
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#define OFF_SBI_SLOT1_CONFIG 0x14
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#define OFF_SBI_SLOT2_CONFIG 0x18
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#define OFF_SBI_SLOT3_CONFIG 0x1c
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#define OFF_SBI_SLOT0_STBUF_CONTROL 0x20
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#define OFF_SBI_SLOT1_STBUF_CONTROL 0x24
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#define OFF_SBI_SLOT2_STBUF_CONTROL 0x28
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#define OFF_SBI_SLOT3_STBUF_CONTROL 0x2c
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#define OFF_SBI_INTR_STATE 0x30
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#define OFF_SBI_INTR_TARGET_ID 0x34
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#define OFF_SBI_INTR_DIAG 0x38
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/*
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* SBI control register setting macros.
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*/
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#define VA_SBI_CNTL(va_sbi) ((va_sbi) + OFF_SBI_CONTROL)
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#define SDTOL_SHFT 17
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#define DFLT_SDTOL 0xD
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#define sbi_set_sdtol(ctl, sdtol) \
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((ctl) | ((sdtol) << SDTOL_SHFT))
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SYS_PHYSADDR_H */
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