239 lines
8.4 KiB
C
Executable File
239 lines
8.4 KiB
C
Executable File
/*
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* Copyright (c) 1991, 1993 by Sun Microsystems, Inc.
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*/
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#ifndef _SYS_CLOCK_H
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#define _SYS_CLOCK_H
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#pragma ident "@(#)clock.h 1.35 94/11/21 SMI"
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#include <sys/devaddr.h>
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#include <sys/spl.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASM
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struct count14 {
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u_int timer_msw; /* also limit14 */
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u_int timer_lsw; /* also counter14 */
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u_int lim14_noreset;
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u_int control;
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u_char filler[0x1000 - 0x10];
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};
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extern volatile struct count14 *v_counter_addr[4];
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extern struct count10 *v_level10clk_addr;
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struct count10 {
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u_int limit10;
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u_int counter10;
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u_int lim10_noreset;
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u_int filler;
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u_int config;
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};
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#ifdef _KERNEL
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extern void set_clk_mode(u_int, u_int);
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extern void start_snooping(int);
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#endif /* _KERNEL */
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#endif /* _ASM */
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#define CTR_LIMIT_BIT 0x80000000 /* limit bit mask */
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#define CTR_USEC_MASK 0x7FFFFC00 /* counter/limit mask */
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#define CTR_USEC_SHIFT 10 /* counter/limit shift */
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#define CTR_USEC_BASE (1 << (CTR_USEC_SHIFT-1))
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/* half a microsecond */
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/*
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* Timer Configuration defines
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*/
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#define TMR0_CONFIG 0x1 /* CPU 0 timer configuration */
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#define TMR1_CONFIG 0x2 /* CPU 1 timer configuration */
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#define TMR2_CONFIG 0x4 /* CPU 2 timer configuration */
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#define TMR3_CONFIG 0x8 /* CPU 3 timer configuration */
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#define TMRALL_CONFIG 0xF /* All configurations */
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/*
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* Definitions for the Mostek 48T02 clock chip. We use this chip as
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* our TOD clock. Clock interrupts are generated by a separate timer
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* circuit.
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*/
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#define YRBASE 68 /* 1968 - what year 0 in chip represents */
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#define NANOSEC 1000000000
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#define ADJ_SHIFT 4 /* used in get_hrestime and _level10 */
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#ifndef _ASM
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struct mostek48T02 {
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volatile u_char clk_ctrl; /* ctrl register */
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volatile u_char clk_sec; /* counter - seconds 0-59 */
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volatile u_char clk_min; /* counter - minutes 0-59 */
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volatile u_char clk_hour; /* counter - hours 0-23 */
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volatile u_char clk_weekday; /* counter - weekday 1-7 */
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volatile u_char clk_day; /* counter - day 1-31 */
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volatile u_char clk_month; /* counter - month 1-12 */
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volatile u_char clk_year; /* counter - year 0-99 */
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};
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#define CLOCK ((struct mostek48T02 *)(V_CLK1ADDR))
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#endif /* _ASM */
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/*
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* Bit masks for various operations and register limits.
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*/
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#define CLK_CTRL_WRITE 0x80
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#define CLK_CTRL_READ 0x40
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#define CLK_CTRL_SIGN 0x20
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#define CLK_STOP 0x80
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#define CLK_KICK 0x80
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#define CLK_FREQT 0x40
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/*
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* These macros were split from sparc/sys/machlock.h because of the
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* way sun4m's cross-call handshake works. If a cross-call happens
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* while one cpu has hres_lock and another is trying to acquire it
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* in its clock interrupt handler; the system will deadlock since
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* the first cpu will never release hres_lock since it's waiting
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* to be released from the cross-call, and the cross-call can't
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* complete because the second cpu is spinning on hres_lock with
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* traps disabled. The fix is to block cross-calls while holding
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* hres_lock.
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*/
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/*
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* CLOCK_LOCK() puts a "ff" in the lowest byte of the hres_lock. The
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* higher three bytes are used as a counter. This lock is acquired
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* around "hrestime" and "timedelta". This lock is acquired to make
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* sure that level10 accounts for changes to this variable in that
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* interrupt itself. The level10 interrupt code also acquires this
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* lock.
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*
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* CLOCK_UNLOCK() increments the lower bytes straight, thus clearing the
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* lock and also incrementing the 3 byte counter. This way GET_HRESTIME()
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* can figure out if the value in the lock got changed or not.
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*/
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#define HRES_LOCK_OFFSET 3
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#define CLOCK_LOCK() \
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lock_set_spl(((lock_t *)&hres_lock) + HRES_LOCK_OFFSET, \
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ipltospl(XC_MED_PIL))
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#define CLOCK_UNLOCK(spl) \
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hres_lock++; \
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(void) splx(spl)
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/*
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* NOTE: the macros below assume that the various time-related variables
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* (hrtime_base, vtrace_time_base, hrestime, timedelta, etc) are all
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* stored together at a 64-byte boundary. The real motivation is cache
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* performance, but here we take advantage of the side effect that all
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* these variables have the same high 22 address bits -- thus, only one
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* sethi is required.
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*/
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/*
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* macro to get high res time in nanoseconds since boot to the register
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* pair outh/outl, using register pair scrh/scrl and nslt for scratch.
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* These must be specified as five distinct registers!
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*
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* WARNING: branches are hand-computed to prevent hidden conflicts with
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* local labels in the caller. If you ever change these macros, make
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* sure you recompute the branch targets.
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*/
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#define GET_HRTIME(outh, outl, scrh, scrl, nslt) \
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/* 1 */ sethi %hi(hrtime_base), scrh; /* time base addr */ \
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ldd [scrh + %lo(hrtime_base)], outh; /* read time base */ \
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ld [scrh + %lo(v_level10clk_addr)], scrl; /* counter addr */\
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ld [scrl + CTR_COUNT10], nslt; /* read counter */ \
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ldd [scrh + %lo(hrtime_base)], scrh; /* re-read time base */\
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sub scrl, outl, scrl; /* low bit diff */ \
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sub scrh, outh, scrh; /* high bit diff */ \
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or scrl, scrh, scrl; /* non-zero iff diff */ \
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sra outh, 31, scrh; /* non-zero iff invalid */\
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orcc scrl, scrh, %g0; /* base changed or invalid? */\
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bne . - 10*4; /* 1b */ /* yes, try again */ \
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addcc nslt, nslt, nslt; /* test & clear limit bit 31 */\
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srl nslt, 7, scrl; /* 2048u / 128 = 16u */ \
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sub nslt, scrl, nslt; /* 2048u - 16u = 2032u */\
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sub nslt, scrl, nslt; /* 2032u - 16u = 2016u */\
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sub nslt, scrl, nslt; /* 2016u - 16u = 2000u */\
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bcc . + 5*4; /* 2f */ /* limit bit not set */ \
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srl nslt, 1, nslt; /* delay: 2000u / 2 = nsec */\
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sethi %hi(nsec_per_tick), scrh; \
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ld [scrh + %lo(nsec_per_tick)], scrh; \
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add nslt, scrh, nslt; /* add 1 tick for limit bit */\
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/* 2 */ addcc outl, nslt, outl; /* add nsec since last tick */\
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addx outh, %g0, outh; /* to hrtime_base */
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/*
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* This macro return the value of hrestime, hrestime_adj and the counter.
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* It reads the value of hres_lock before and after loading the above
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* values. If the lock value changed in the meanwhile (i.e. level10 is/was
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* being processed on another processor or someone updated the hrestime_adj
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* and/or hrestime), the macro reads the value again.
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*
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* It assumes that the adj and hrest are register pairs. This macro
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* is called from trap (0x27) in sparc_subr.s.
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*/
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#define GET_HRESTIME(out, scr, scr1, adj, hrest) \
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/* 1 */ sethi %hi(hres_lock), out; \
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ld [out + %lo(hres_lock)], scr1; /* load clock lock */ \
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ld [out + %lo(v_level10clk_addr)], out; /* counter addr */ \
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ld [out + CTR_COUNT10], out; /* read counter */ \
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addcc out, out, out; /* test & clear limit bit 31 */\
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srl out, 7, scr; /* 2048u / 128 = 16u */ \
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sub out, scr, out; /* 2048u - 16u = 2032u */\
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sub out, scr, out; /* 2032u - 16u = 2016u */\
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sub out, scr, out; /* 2016u - 16u = 2000u */\
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bcc . + 5*4; /* 2f */ /* limit bit not set */ \
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srl out, 1, out; /* delay: 2000u / 2 = nsec */\
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sethi %hi(nsec_per_tick), scr; \
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ld [scr + %lo(nsec_per_tick)], scr; \
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add out, scr, out; /* add 1 tick for limit bit */ \
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/* 2 */ sethi %hi(hrtime_base), scr; /* scr = hi bits for all */\
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ld [scr + %lo(hres_last_tick)], adj; \
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sub out, adj, out; \
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ldd [scr + %lo(hrestime)], hrest; /* load hrestime */ \
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ldd [scr + %lo(hrestime_adj)], adj; /* load hrestime_adj */ \
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ld [scr + %lo(hres_lock)], scr; /* load clock lock */ \
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andn scr1, 1, scr1; /* so cmp can detect lock still held */ \
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cmp scr1, scr; \
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bne . - 22*4; /* 1b */ \
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nop;
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/*
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* This macro is here to support vtrace 3.x, which is microsecond-based.
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* This will go away with vtrace 4.0.0, which will be nanosecond-based.
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*/
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#define GET_VTRACE_TIME(outl, scr1, scr2) \
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/* 1 */ sethi %hi(vtrace_time_base), scr1; /* time base addr */ \
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ld [scr1 + %lo(vtrace_time_base)], outl; /* read time base */\
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ld [scr1 + %lo(v_level10clk_addr)], scr2; /* counter addr */\
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ld [scr2 + CTR_COUNT10], scr2; /* read counter */ \
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ld [scr1 + %lo(vtrace_time_base)], scr1; /* re-read time base */\
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sub outl, scr1, scr1; /* scr1 < 0 iff update */\
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srl scr1, 31, scr1; /* scr1 = update ? 1 : 0 */\
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or scr1, outl, scr1; /* scr1 & 1 iff update */\
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andcc scr1, 1, %g0; /* update in progress? */\
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bnz . - 9*4; /* 1b */ /* yes, try again */ \
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addcc scr2, scr2, scr2; /* test & clear limit bit 31 */\
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bcc . + 5*4; /* 2f */ /* limit bit not set */ \
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srl scr2, CTR_USEC_SHIFT + 1, scr2; /* delay: convert to usec */\
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sethi %hi(usec_per_tick), scr1; \
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ld [scr1 + %lo(usec_per_tick)], scr1; \
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add scr2, scr1, scr2; /* add 1 tick for limit bit */\
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/* 2 */ add outl, scr2, outl; /* add counter value */
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#ifdef __cplusplus
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}
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#endif
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#endif /* !_SYS_CLOCK_H */
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