228 lines
8.7 KiB
C
Executable File
228 lines
8.7 KiB
C
Executable File
/*
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* Copyright (c) 1991, by Sun Microsystems, Inc.
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*/
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#ifndef _SYS_SYSIOERR_H
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#define _SYS_SYSIOERR_H
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#pragma ident "@(#)sysioerr.h 1.7 95/08/31 SMI"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Sbus error interrupt priorities
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*/
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#define SBUS_UE_PIL 12
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#define SBUS_CE_PIL 11
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#define SBUS_ERR_PIL 12
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#define SBUS_THERMAL_PIL 9
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/*
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* SBus error register offsets and INOs
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*/
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#define SYSIO_CSR_OFFSET 0x0010
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#define SBUS_ECC_CR_OFFSET 0x0020
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#define SBUS_UE_AFSR_OFFSET 0x0030
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#define SBUS_UE_AFAR_OFFSET 0x0038
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#define SBUS_CE_AFSR_OFFSET 0x0040
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#define SBUS_CE_AFAR_OFFSET 0x0048
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#define SBUS_CSR_OFFSET 0x2000
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#define SBUS_ERR_AFSR_OFFSET 0x2010
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#define SBUS_ERR_AFAR_OFFSET 0x2018
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#define SBUS_UE_CLR_OFFSET 0x3870
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#define SBUS_CE_CLR_OFFSET 0x3878
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#define SBUS_ERR_CLR_OFFSET 0x3880
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#define SBUS_UE_INO 0x0034
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#define SBUS_CE_INO 0x0035
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#define SBUS_ERR_INO 0x0036
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/*
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* SBus map register offsets
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*/
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#define SBUS_SLOT0_MAP_OFFSET 0x2C00
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#define SBUS_SLOT1_MAP_OFFSET 0x2C08
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#define SBUS_SLOT2_MAP_OFFSET 0x2C10
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#define SBUS_SLOT3_MAP_OFFSET 0x2C18
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#define SBUS_SCSI_MAP_OFFSET 0x3000
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#define SBUS_ENET_MAP_OFFSET 0x3008
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#define SBUS_PARA_MAP_OFFSET 0x3010
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#define SBUS_AUDIO_MAP_OFFSET 0x3018
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#define SBUS_POWER_MAP_OFFSET 0x3020
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#define SBUS_K_M_S_MAP_OFFSET 0x3028
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#define SBUS_FLOPPY_MAP_OFFSET 0x3030
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#define SBUS_THERMAL_MAP_OFFSET 0x3038
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#define SBUS_KEYBD_MAP_OFFSET 0x3040
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#define SBUS_MOUSE_MAP_OFFSET 0x3048
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#define SBUS_SERIAL_MAP_OFFSET 0x3050
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#define SBUS_CLK0_MAP_OFFSET 0x3060
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#define SBUS_CLK1_MAP_OFFSET 0x3068
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#define SBUS_UE_MAP_OFFSET 0x3070
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#define SBUS_CE_MAP_OFFSET 0x3078
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#define SBUS_ERR_MAP_OFFSET 0x3080
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#define SBUS_WAKEUP_MAP_OFFSET 0x3088
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#define SBUS_GRAPHIC_MAP_OFFSET 0x3090
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#define SBUS_UPA1_MAP_OFFSET 0x3098
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#define SBUS_UPA2_MAP_OFFSET 0x8000
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#define SBUS_MAP_REGISTERS 24
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/*
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* Bits of Sun5 SYSIO Control/Status Register
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*/
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#define SYSIO_IMPL 0xF000000000000000ULL /* implementation number */
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#define SYSIO_VER 0x0F00000000000000ULL /* revision number */
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#define SYSIO_MID 0x00F8000000000000ULL /* UPA mid for SYSIO */
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#define SYSIO_INTGN 0x0007C00000000000ULL /* interrupt group number */
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#define SYSIO_APCKEN 0x0000000000000008ULL /* address parity check enable */
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#define SYSIO_APERR 0x0000000000000004ULL /* system address parity error */
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#define SYSIO_IAP 0x0000000000000002ULL /* invert UPA address parity */
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#define SYSIO_MODE 0x0000000000000001ULL /* speed of SYSIO clock */
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/*
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* Bits of Sun5 SBus ECC Control Register
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*/
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#define SECR_ECC_EN 0x8000000000000000ULL /* enable ECC checking */
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#define SECR_UE_INTEN 0x4000000000000000ULL /* enable UE_INT interrupt */
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#define SECR_CE_INTEN 0x2000000000000000ULL /* enable CE_INT interrupt */
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/*
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* Bits of Sun5 SBus UE Asynchronous Fault Status Register
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*/
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#define SB_UE_AFSR_P_PIO 0x8000000000000000ULL /* primary UE, PIO access */
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#define SB_UE_AFSR_P_DRD 0x4000000000000000ULL /* primary UE, DVMA read */
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#define SB_UE_AFSR_P_DWR 0x2000000000000000ULL /* primary UE, DVMA write */
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#define SB_UE_AFSR_P 0xE000000000000000ULL /* primary UE */
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#define SB_UE_AFSR_S_PIO 0x1000000000000000ULL /* secondary UE, PIO access */
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#define SB_UE_AFSR_S_DRD 0x0800000000000000ULL /* secondary UE, DVMA read */
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#define SB_UE_AFSR_S_DWR 0x0400000000000000ULL /* secondary UE, DVMA write */
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#define SB_UE_AFSR_S 0x1C00000000000000ULL /* secondary UE */
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#define SB_UE_AFSR_OFF 0x0000E00000000000ULL /* offset of dword w/pri. UE */
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#define SB_UE_AFSR_SIZE 0x00001C0000000000ULL /* 2**size of bad transfer */
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#define SB_UE_AFSR_MID 0x000003E000000000ULL /* master ID for pri. error */
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#define SB_UE_AFSR_ISAP 0x0000001000000000ULL /* system parity error */
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/*
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* Shifts for SBus Sysio UE Asynchronous Fault Status Register
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*/
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#define SB_UE_DW_SHIFT (45)
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#define SB_UE_SIZE_SHIFT (42)
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#define SB_UE_MID_SHIFT (41)
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/*
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* Bits of Fusion Desktop SBus UE Asynchronous Fault Address Register
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*/
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#define SB_UE_AFAR_PA 0x000001FFFFFFFFFF /* PA<40:0>: physical address */
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/*
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* Bits of Sun5 SBus CE Asynchronous Fault Status Register
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*/
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#define SB_CE_AFSR_P_PIO 0x8000000000000000ULL /* primary CE, PIO access */
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#define SB_CE_AFSR_P_DRD 0x4000000000000000ULL /* primary CE, DVMA read */
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#define SB_CE_AFSR_P_DWR 0x2000000000000000ULL /* primary CE, DVMA write */
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#define SB_CE_AFSR_P 0xE000000000000000ULL /* primary CE */
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#define SB_CE_AFSR_S_PIO 0x1000000000000000ULL /* secondary CE, PIO access */
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#define SB_CE_AFSR_S_DRD 0x0800000000000000ULL /* secondary CE, DVMA read */
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#define SB_CE_AFSR_S_DWR 0x0400000000000000ULL /* secondary CE, DVMA write */
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#define SB_CE_AFSR_S 0x1C00000000000000ULL /* secondary CE */
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#define SB_CE_AFSR_SYND 0x00FF000000000000ULL /* CE syndrome bits */
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#define SB_CE_AFSR_OFF 0x0000E00000000000ULL /* offset of dword w/pri. CE */
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#define SB_CE_AFSR_SIZE 0x00001C0000000000ULL /* 2**size of failed transfer */
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#define SB_CE_AFSR_MID 0x000003E000000000ULL /* master ID for primary error */
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/*
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* Shifts for Sun5 SBus CE Asynchronous Fault Status Register
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*/
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#define SB_CE_SYND_SHIFT (48)
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#define SB_CE_OFFSET_SHIFT (45)
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#define SB_CE_SIZE_SHIFT (42)
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#define SB_CE_MID_SHIFT (41)
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/*
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* Bits of Sun5 Fusion Desktop SBus CE Asynchronous Fault Address Register
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* Note: Fusion Desktop does not support E_SYND2.
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*/
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#define SB_CE_E_SYND2 0xFF00000000000000ULL /* syndrome of prim. CE */
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#define SB_CE_AFAR_PA 0x000001FFFFFFFFFFULL /* PA<40:0>: physical address */
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/*
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* Shift for Sun5 SBus CE Asynchronous Fault Address Register
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*/
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#define SB_CE_SYND2_SHIFT (56)
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/*
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* Bits of Sun5 SBus Control and Status Register
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* See Fusion Desktop System Spec. Table 3-63 for details on slots 13-15
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*/
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#define SB_CSR_IMPL 0xF000000000000000ULL /* host adapter impl. number */
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#define SB_CSR_REV 0x0F00000000000000ULL /* host adapter rev. number */
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#define SB_CSR_DPERR_S14 0x0020000000000000ULL /* SBus slot 14 aka Happy Meal */
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#define SB_CSR_DPERR_S13 0x0010000000000000ULL /* SBus slot 13 aka APC */
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#define SB_CSR_DPERR_S3 0x0008000000000000ULL /* SBus slot 3 DVMA parity err */
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#define SB_CSR_DPERR_S2 0x0004000000000000ULL /* SBus slot 2 DVMA parity err */
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#define SB_CSR_DPERR_S1 0x0002000000000000ULL /* SBus slot 1 DVMA parity err */
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#define SB_CSR_DPERR_S0 0x0001000000000000ULL /* SBus slot 0 DVMA parity err */
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#define SB_CSR_PIO_PERRS 0x00007F0000000000ULL /* SBus parity errors */
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#define SB_CSR_PPERR_S15 0x0000400000000000ULL /* SBus slot 15 aka slavio */
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#define SB_CSR_PPERR_S14 0x0000200000000000ULL /* SBus slot 14 aka Happy Meal */
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#define SB_CSR_PPERR_S13 0x0000100000000000ULL /* SBus slot 13 aka APC */
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#define SB_CSR_PPERR_S3 0x0000080000000000ULL /* SBus slot 3 PIO parity err */
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#define SB_CSR_PPERR_S2 0x0000040000000000ULL /* SBus slot 2 PIO parity err */
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#define SB_CSR_PPERR_S1 0x0000020000000000ULL /* SBus slot 1 PIO parity err */
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#define SB_CSR_PPERR_S0 0x0000010000000000ULL /* SBus slot 0 PIO parity err */
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#define SB_CSR_FAST_SBUS 0x0000000000000400ULL /* shorten PIO access latency */
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#define SB_CSR_WAKEUP_EN 0x0000000000000200ULL /* power-management bit */
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#define SB_CSR_ERRINT_EN 0x0000000000000100ULL /* enable intr. for SBus errs */
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#define SB_CSR_ARBEN_MAC 0x0000000000000020ULL /* enable DVMA for Macio */
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#define SB_CSR_ARBEN_APC 0x0000000000000010ULL /* enable DVMA for APC */
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#define SB_CSR_ARBEN_SLT 0x000000000000000FULL /* enable DVMA for SBus slots */
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/*
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* Shifts for Sun5 SBus Control and Status Register
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*/
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#define SB_CSR_IMPL_SHIFT (60)
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#define SB_CSR_REV_SHIFT (56)
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#define SB_CSR_DVMA_PERR_SHIFT (48)
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#define SB_CSR_PIO_PERR_SHIFT (40)
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/*
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* Bits of Sun5 SBus Asynchronous Fault Status Register
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*/
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#define SB_AFSR_P_ERRS 0xE000000000000000ULL /* primary errors */
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#define SB_AFSR_P_LE 0x8000000000000000ULL /* primary LATE_ERR */
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#define SB_AFSR_P_TO 0x4000000000000000ULL /* primary SBus TIMEOUT */
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#define SB_AFSR_P_BERR 0x2000000000000000ULL /* primary SBus ERR ack */
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#define SB_AFSR_S_ERRS 0x1C00000000000000ULL /* secondary errors */
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#define SB_AFSR_S_LE 0x1000000000000000ULL /* secondary LATE_ERR */
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#define SB_AFSR_S_TO 0x0800000000000000ULL /* secondary SBus TIMEOUT */
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#define SB_AFSR_S_BERR 0x0400000000000000ULL /* secondary SBus ERR ack */
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#define SB_AFSR_RD 0x0000800000000000ULL /* primary error was READ op. */
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#define SB_AFSR_SIZE 0x00001C0000000000ULL /* 2**size of failed transfer */
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#define SB_AFSR_MID 0x000003E000000000ULL /* master ID for primary error */
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/*
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* Shifts for Sun5 SBus Asynchronous Fault Status Register
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*/
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#define SB_AFSR_SIZE_SHIFT (42)
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#define SB_AFSR_MID_SHIFT (37)
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/*
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* Bits of Fusion Desktop SBus Asynchronous Fault Address Register
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*/
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#define SB_AFAR_PA 0x000001FFFFFFFFFFULL /* PA<40:0>: physical address */
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/*
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* Function prototypes
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*/
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extern int
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sysio_err_init(struct sbus_soft_state *softsp, int address);
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extern int
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sysio_err_resume_init(struct sbus_soft_state *softsp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SYS_SYSIOERR_H */
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