1083 lines
37 KiB
C
1083 lines
37 KiB
C
/*
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* @(#)sm.c 1.1 92/07/30 Copyright (c) 1988 by Sun Microsystems, Inc.
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*
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* Emulex ESP SCSI (low-level) driver
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*
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*
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* 3/89 KSAM Send back exact amount of transferred bytes for
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* Front-load 1/2 tape per 4.0.3 FCS release.
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* 11/88 KSAM Add in support for 4.0.3 beta release
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* 9/88 KSAM Change to match the new 4.0 REV-2 SCSI structure
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* 8/88 KSAM Add in Stingray support
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* 5/88 KSAM initial written
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*/
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#if (defined sun4) || (defined sun3x)
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#define REL4 /* enable release 4.00 mods */
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#ifdef notdef
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#define SMEPRINT /* Allow error printfs */
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#define SMDEBUG /* Allow compiling of debug code */
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#endif notdef
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#ifdef REL4
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#include <sys/types.h>
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#include <sys/buf.h>
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#include <sun/dklabel.h>
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#include <sun/dkio.h>
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#include <stand/smreg.h>
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#include <stand/scsi.h>
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#include <stand/saio.h>
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#else REL4
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#include "../h/types.h"
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#include "../h/buf.h"
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#include "../sun/dklabel.h"
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#include "../sun/dkio.h"
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#include "smreg.h"
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#include "scsi.h"
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#include "saio.h"
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#endif REL4
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#ifdef REL4
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#include <mon/sunromvec.h>
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#include <mon/idprom.h>
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#else REL4
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#include "../mon/sunromvec.h"
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#include "../mon/idprom.h"
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#endif REL4
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/* for bring-up stage, print all error messages */
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#ifdef SMDEBUG
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int sm_debug = 1; /* normally enable error-printfs */
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/* Handy debugging 0, 1, and 2 argument printfs, NEED "sm_debug" */
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#define DPRINTF(str) \
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if (sm_debug > 2) printf(str)
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#define DPRINTF1(str, arg1) \
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if (sm_debug > 3) printf(str,arg1)
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#define DPRINTF2(str, arg1, arg2) \
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if (sm_debug > 4) printf(str,arg1,arg2)
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#define DEBUG_DELAY(cnt) \
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if (sm_debug > 5) DELAY(cnt)
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#define EPRINTF(str) \
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if (sm_debug) printf(str)
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#define EPRINTF1(str, arg1) \
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if (sm_debug) printf(str,arg1)
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#define EPRINTF2(str, arg1, arg2) \
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if (sm_debug) printf(str,arg1,arg2)
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#else SMDEBUG
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#define DEBUG_DELAY(cnt)
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#define DPRINTF(str)
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#define DPRINTF1(str, arg1)
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#define DPRINTF2(str, arg1, arg2)
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#ifdef SMEPRINT
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#define EPRINTF(str) printf(str)
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#define EPRINTF1(str, arg1) printf(str,arg1)
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#define EPRINTF2(str, arg1, arg2) printf(str,arg1,arg2)
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#else
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#define EPRINTF(str)
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#define EPRINTF1(str, arg1)
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#define EPRINTF2(str, arg1, arg2)
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#endif SMEPRINT
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#endif SMDEBUG
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/*
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* Low-level routines common to all devices on the SCSI bus.
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*/
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/*
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* Interface to the routines in this module is via a second "h_sip"
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* structure contained in the caller's local variables.
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*
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* This "h_sip" must be initialized with h_sip->smboottab = sm_driver
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* and must then be devopen()ed before any I/O can be done.
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*
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* The device must be closed with devclose().
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*/
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/*
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* The interfaces we export
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*/
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extern int scsi_debug;
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extern char *devalloc();
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extern char *resalloc();
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extern int nullsys();
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extern u_char sc_cdb_size[];
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int smopen(), smdoit(), sm_reset();
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/* special snapshot data structure for sm.c */
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struct sm_snap smreg_info;
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int scsi_reset = ZERO;
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#define FAIL -1
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#define OK 0
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/*
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* Open the SCSI host adapter.
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* if found, return (OK=0), FAIL=-1 otherwise.
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*/
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int
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smopen(h_sip)
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register struct host_saioreq *h_sip;
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{
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register struct scsi_sm_reg *smr;
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register struct udc_table *dvma;
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register int i, j;
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struct idprom id;
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int base;
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int scsi_nstd;
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enum MAPTYPES space;
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u_long dvmastat;
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if (idprom(IDFORM_1, &id) == IDFORM_1) {
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space = MAP_OBIO;
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scsi_nstd = 1;
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DPRINTF1("smopen: id.machine= %x\n", id.id_machine);
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switch (id.id_machine) {
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#ifdef sun3x
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case IDM_SUN3X_HYDRA:
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base = HYDRA_SCSI_BASE;
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i = HYDRA;
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break;
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#endif sun3x
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#ifdef sun4
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case IDM_SUN4_STINGRAY:
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base = STINGRAY_SCSI_BASE;
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i = STINGRAY;
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break;
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#endif sun4
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default:
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EPRINTF1("smopen: unknown machine type= %x\n",
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id.id_machine);
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/* other configuration not supported */
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return(FAIL);
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}
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} else {
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/* unknown id type not supported */
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EPRINTF1("smopen: UNKNOWN id type= %x\n",
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idprom(IDFORM_1, &id));
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return(FAIL);
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}
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DPRINTF1("smopen: ctlr= %x\n", h_sip->ctlr);
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/* get base address of registers */
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if (h_sip->ctlr < scsi_nstd) {
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h_sip->ctlr = base + (h_sip->ctlr * SM_SIZE);
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} else {
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EPRINTF2("smopen: invalid cltr_num= %x, busid= %x\n",
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h_sip->ctlr, h_sip->unit);
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return(FAIL);
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}
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DPRINTF1("smopen: REG_base= %x\n", h_sip->ctlr);
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DEBUG_DELAY(1000000);
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/* now map it in */
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h_sip->devaddr = devalloc(space, h_sip->ctlr,
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sizeof(struct scsi_sm_reg));
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if (h_sip->devaddr == ZERO) {
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EPRINTF("smopen: Can not allocate ESP space\n");
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return(FAIL);
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}
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DPRINTF1("smopen: sm_addr = %x\n", h_sip->devaddr);
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/* allocate dma resources for on-board host */
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h_sip->dmaaddr = h_sip->devaddr + STINGRAY_DMA_OFFSET;
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smr = (struct scsi_sm_reg *)h_sip->devaddr;
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dvma = (struct udc_table *)h_sip->dmaaddr;
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#ifdef sun4
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DPRINTF1("smopen: peeking DVMA's ctl_stat @ %x\n",
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&dvma->ctl_stat);
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/* I only modify the lib/sun4/probe.s */
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if ((peekl((long *)&(dvma->ctl_stat))) == -1) {
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EPRINTF1("smopen: peek on DVMA-scsi dma_addr= %x FAILED\n",
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&(dvma->ctl_stat));
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DEBUG_DELAY(1000000);
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return(FAIL);
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}
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DPRINTF1("smopen: DVMA exists, reg_stat= %x\n", dvma->ctl_stat);
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#endif sun4
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DEBUG_DELAY(1000000);
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dvmastat = dvma->ctl_stat;
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if (dvmastat & DVMA_REQPEND) {
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EPRINTF1("smopen: DVMA-scsi req_pend stuck, stat= %x\n",
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dvmastat);
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return(FAIL);
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}
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if (dvmastat & DVMA_RESET) {
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DPRINTF1("smopen: DVMA reset asserted, stat= %x\n", i);
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/* attempt to clear it, if not successful, error return */
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dvma->ctl_stat = ZERO;
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for (i = 0; i < LOOP_2MSEC; i++);
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dvmastat = dvma->ctl_stat;
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if (dvmastat & DVMA_RESET) {
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EPRINTF1("smopen: DVMA-scsi reset stuck, stat= %x\n",
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dvmastat);
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return(FAIL);
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}
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DPRINTF1("smopen: deasserted DVMA reset, stat= %x\n", i);
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}
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/* write/read/compare DVMA 's address reg */
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dvmastat = DVMA_TPATTERN;
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dvma->dma_addr = dvmastat;
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DPRINTF2("smopen: DVMA test, wr= %x, rd= %x\n",
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dvmastat, dvma->dma_addr);
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if (dvma->dma_addr != dvmastat) {
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EPRINTF2("smopen: DVMA-scsi mismatched dma_addr, wr= %x, rd= %x\n",
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i, dvma->dma_addr);
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return(FAIL);
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}
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dvma->dma_addr = ZERO;
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DPRINTF2("smopen: DVMA-scsi PASSED, stat= %x, addr= %x\n",
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dvma->ctl_stat, dvma->dma_addr);
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DEBUG_DELAY(1000000);
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/* check existence and operational status of DVMA before */
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/* checking on ESP. If scsi_reset in DVMA is asserted, the */
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/* ESP register will not be accessible and DVMA itself is */
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/* NOT in a operational state */
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/* Check ESP existence -- peek on "ESP reg_xcnt_lo" */
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#ifdef sun4
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DPRINTF1("smopen: peeking ESP's xcnt_lo @ %x\n",
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&ESP_RD.xcnt_lo);
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/* I only modify the lib/sun4/probe.s */
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if ((peekc((u_char *)&(ESP_RD.xcnt_lo))) == -1) {
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EPRINTF1("smopen: peek on ESP's addr= %x FAILED\n",
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&ESP_RD.xcnt_lo);
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DEBUG_DELAY(1000000);
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return(FAIL);
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}
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DPRINTF1("smopen: ESP exists, reg_conf= %x\n", ESP_RD.conf);
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#endif sun4
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/* perform a simple write, read and compare validation test to
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"ESP reg_conf". If error, return */
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i = 0x55;
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ESP_WR.conf = i;
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j = ESP_RD.conf;
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DPRINTF2("smopen: ESP wr= %x, rd= %x\n", i, j);
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if ((u_char)i != (u_char)j) {
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DEBUG_DELAY(1000000);
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return(FAIL);
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}
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i = 0xaa;
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ESP_WR.conf = i;
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j = ESP_RD.conf;
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DPRINTF2("smopen: ESP wr: = %x, rd= %x\n", i, j);
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DEBUG_DELAY(1000000);
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if ((u_char)i != (u_char)j) {
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DEBUG_DELAY(1000000);
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return(FAIL);
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}
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i = ZERO;
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ESP_WR.conf = i;
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j = ESP_RD.conf;
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if ((u_char)i != (u_char)j) {
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DPRINTF2("smopen: ESP FAILED, wr= %x, rd= %x\n", i, j);
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DEBUG_DELAY(1000000);
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return(FAIL);
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}
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/* Perform a simple write, read & compare validation test to ESP_II */
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i = ESP_TPATTERN;
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ESP_WR.conf2 = i; /* write */
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j = ESP_RD.conf2; /* read */
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if ((u_char)i == (u_char)j) { /* compare */
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ESP_WR.conf2 = ZERO; /* make ESP 2 function as ESP */
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DPRINTF("smopen: ESP_2 found, config to ESP\n");
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}
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else
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DPRINTF("smopen: ESP_2 not found\n");
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DEBUG_DELAY(1000000);
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/* set all the routine pointers */
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DPRINTF("smopen: setting doit() pointer\n");
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h_sip->doit = smdoit;
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h_sip->reset = sm_reset;
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if (scsi_reset == ZERO) {
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/* need to reset SCSI bus when call from le() boot, since */
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/* firmware will not call scsi driver to reset the bus */
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sm_reset(h_sip, RESET_ALL_SCSI);
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scsi_reset++;
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}
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else {
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sm_reset(h_sip, RESET_INT_ONLY);
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}
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DPRINTF1("smopen: done, smr= %x\n", smr);
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return(OK); /* successfully opened */
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}
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/*
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* Write a command to the SCSI bus.
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*
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* The supplied h_sip is the one opened by smopen().
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* DMA is done based on h_sip->ma and h_sip->cc.
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*
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* Returns -1 for error, otherwise returns the residual count
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*
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* FIXME, this must be accessed via a boottab vector,
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* to allow host adap to switch.
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* Must pass cdb, scb in h_sip somewhere...
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*/
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int
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smdoit(cdb, scb, h_sip)
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struct scsi_cdb *cdb;
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struct scsi_scb *scb;
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struct host_saioreq *h_sip;
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{
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register struct scsi_sm_reg *smr;
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register struct sm_snap *smsnap = &smreg_info;
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register struct udc_table *dvma;
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register u_char *cp;
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register int i, size;
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u_long toutcnt;
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/* get to scsi control logic registers */
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smr = (struct scsi_sm_reg *)h_sip->devaddr;
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dvma = (struct udc_table *)h_sip->dmaaddr;
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DPRINTF("smdoit: POLL/NO_disconnect mode\n");
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cp = (u_char *)cdb;
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size = sc_cdb_size[CDB_GROUPID(*cp)];
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/* Write "ESP reg_fifo" with all command bytes */
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DPRINTF("smdoit: cmd byte=");
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for (i = 0; i < size; i++) {
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DPRINTF1(" %x", *cp);
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ESP_WR.fifo_data = *cp++;
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}
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DPRINTF1("\nsmdoit: fifo_flag @= %x\n", ESP_RD.fifo_flag);
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DEBUG_DELAY(1000000);
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DPRINTF1("smdoit: ready to send cmd= %x\n", cdb->scc_cmd);
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switch (cdb->scc_cmd) {
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case SC_READ:
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case SC_REQUEST_SENSE:
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case SC_INQUIRY:
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case SC_MODE_SENSE:
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smsnap->sync_chk = SM_RECV_DATA;
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break;
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case SC_WRITE:
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case SC_MODE_SELECT:
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case SC_WRITE_FILE_MARK:
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case SC_WRITE_VERIFY:
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smsnap->sync_chk = SM_SEND_DATA;
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break;
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default:
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smsnap->sync_chk = SM_NO_DATA;
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}
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/* clear some status */
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smsnap->cur_err = (smsnap->scsi_status = ZERO);
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smsnap->cur_retry = ZERO;
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smsnap->cur_state = STATE_SEL_REQ;
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ESP_WR.timeout = DEF_TIMEOUT;
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ESP_WR.busid = h_sip->unit; /* target SCSI ID */
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DPRINTF1("smdoit: selecting target= %x\n", h_sip->unit);
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DEBUG_DELAY(1000000);
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toutcnt = LOOP_CMDTOUT;
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ESP_WR.cmd = CMD_SEL_NOATN; /* NO identify message */
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while ((--toutcnt) && (smsnap->cur_err == ZERO) &&
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(smsnap->cur_state != STATE_FREE)) {
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/* poll on ESP_INT thru DVMA status reg */
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if (dvma->ctl_stat & DVMA_INTPEND) {
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sm_intr(h_sip);
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toutcnt = LOOP_CMDTOUT;
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}
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}
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DPRINTF2("smdoit: err= %x, state= %x\n",
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smsnap->cur_err, smsnap->cur_state);
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DPRINTF2("smdoit: resid= %x, status= %x\n",
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h_sip->cc, smsnap->esp_stat);
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cp = (u_char *)scb;
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*cp = smsnap->scsi_status; /* return scsi bus status */
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DPRINTF1("smdoit: done, bus_status= %x\n", smsnap->scsi_status);
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DEBUG_DELAY(1000000);
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if ((toutcnt == ZERO) || (smsnap->cur_err)) {
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EPRINTF2("sm_cmd: CMD_TIMED-OUT, err= %x, toutcnt= %x\n",
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smsnap->cur_err, toutcnt);
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EPRINTF2("sm_cmd: cmd= %x, esp_stat= %x\n",
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cdb->scc_cmd, ESP_RD.stat);
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EPRINTF2("sm_cmd: state= %x, cc= %x\n",
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smsnap->cur_state, h_sip->cc);
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EPRINTF2("sm_cmd: dma_stat= %x, dma_addr= %x\n",
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dvma->ctl_stat, dvma->dma_addr);
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DEBUG_DELAY(1000000);
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return(FAIL);
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}
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return (h_sip->cc); /* successful */
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}
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static int
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sm_dma_setup(h_sip)
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register struct host_saioreq *h_sip;
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{
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register struct scsi_sm_reg *smr;
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register struct udc_table *dvma;
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register struct sm_snap *smsnap = &smreg_info;
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#ifdef SMDEBUG
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u_char *ptr;
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int i;
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#endif SMDEBUG
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if ((h_sip->cc == ZERO) || (smsnap->sync_chk == SM_NO_DATA)) {
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DPRINTF1("sm_dma_setup: return due to xfr_cnt= %x\n",
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h_sip->cc);
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return;
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}
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/* get to scsi control logic registers */
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smr = (struct scsi_sm_reg *)h_sip->devaddr;
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dvma = (struct udc_table *)h_sip->dmaaddr;
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#ifdef SMDEBUG
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DPRINTF1("sm_dma_setup: ORG_addr= %x, data= ", h_sip->ma);
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ptr = (u_char *)h_sip->ma;
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for (i = 0; i < 20; i++, ptr++) {
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DPRINTF1(" %x ", *ptr);
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}
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DPRINTF1("\nsm_dma_setup: ORG_cnt= %x\n", h_sip->cc);
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#endif SMDEBUG
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dvma->dma_addr = (u_long)h_sip->ma; /* set dma address */
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ESP_WR.xcnt_lo = (u_char)h_sip->cc;
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ESP_WR.xcnt_hi = (u_char)(h_sip->cc >> 8);
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ESP_WR.cmd = CMD_NOP | CMD_DMA; /* NOP needed */
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DPRINTF2("sm_dma_setup: xcnt_lo= %x, xcnt_hi= %x\n",
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ESP_RD.xcnt_lo, ESP_RD.xcnt_hi);
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/* enable DMA */
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if (smsnap->sync_chk == SM_SEND_DATA) {
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DPRINTF("sm_cmd: setting a write to SCSI\n");
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dvma->ctl_stat |= DVMA_ENDVMA;
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dvma->ctl_stat &= ~DVMA_WRITE;
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}
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else {
|
|
DPRINTF("sm_cmd: setting a read to SCSI\n");
|
|
dvma->ctl_stat |= DVMA_ENDVMA | DVMA_WRITE;
|
|
}
|
|
DEBUG_DELAY(1000000);
|
|
}
|
|
|
|
/*
|
|
* Reset some register information after a dma operation.
|
|
*/
|
|
static int
|
|
sm_dma_cleanup(h_sip, espstat)
|
|
register struct host_saioreq *h_sip;
|
|
u_char espstat;
|
|
{
|
|
register struct scsi_sm_reg *smr;
|
|
register struct udc_table *dvma;
|
|
register struct sm_snap *smsnap = &smreg_info;
|
|
register int i;
|
|
u_long toutcnt;
|
|
u_short dma_cnt, esp_cnt, xfrcnt, fifo_cnt, req_cnt;
|
|
#ifdef SMDEBUG
|
|
u_char *ptr;
|
|
|
|
DPRINTF1("sm_dma_cleanup: ORG_addr= %x, NEW_data= ", h_sip->ma);
|
|
ptr = (u_char *)h_sip->ma;
|
|
for (i = 0; i < 20; i++, ptr++) {
|
|
DPRINTF1(" %x ", *ptr);
|
|
}
|
|
DPRINTF1("\nsm_dma_cleanup: ORG_cnt= %x\n", h_sip->cc);
|
|
#endif SMDEBUG
|
|
|
|
req_cnt = h_sip->cc;
|
|
if ((req_cnt == ZERO) || (smsnap->sync_chk == SM_NO_DATA)) {
|
|
DPRINTF2("sm_dma_setup: return, xfr_cnt= %x, stat= %x\n",
|
|
req_cnt, espstat);
|
|
return(ZERO);
|
|
}
|
|
/* get to scsi control logic registers */
|
|
smr = (struct scsi_sm_reg *)h_sip->devaddr;
|
|
|
|
/* get to scsi control logic registers */
|
|
smr = (struct scsi_sm_reg *)h_sip->devaddr;
|
|
dvma = (struct udc_table *)h_sip->dmaaddr;
|
|
|
|
dvma->ctl_stat &= ~DVMA_ENDVMA;
|
|
toutcnt = dvma->ctl_stat;
|
|
DPRINTF2("sm_dma_cleanup: dvma_stat= %x, addr= %x\n",
|
|
toutcnt, dvma->dma_addr);
|
|
DEBUG_DELAY(1000000);
|
|
if (toutcnt & DVMA_REQPEND) {
|
|
toutcnt = LOOP_4SEC; /* must be over 2sec */
|
|
while ((dvma->ctl_stat & DVMA_REQPEND) && (--toutcnt)) ;
|
|
if (toutcnt == ZERO) {
|
|
EPRINTF1("sm_dma_cleanup: DVMA-scsi REQ_PEND struck, stat= %x\n",
|
|
dvma->ctl_stat);
|
|
smsnap->cur_err = SE_REQPEND;
|
|
return(1);
|
|
}
|
|
}
|
|
|
|
if (smsnap->sync_chk == SM_RECV_DATA) {
|
|
DPRINTF("sm_dma_cleanup: send DVMA_drain\n");
|
|
DEBUG_DELAY(1000000);
|
|
dvma->ctl_stat |= DVMA_DRAIN; /* send DRAIN anyway */
|
|
i = LOOP_2MSEC;
|
|
while ((dvma->ctl_stat & DVMA_DRAIN) && (--i));
|
|
if (i == ZERO) {
|
|
EPRINTF1("sm_dma_cleanup: DVMA-scsi drain stuck, stat= %x\n",
|
|
dvma->ctl_stat);
|
|
smsnap->cur_err = SE_DVMAERR;
|
|
dvma->ctl_stat |= DVMA_FLUSH;
|
|
dvma->ctl_stat &= ~(DVMA_ENDVMA | DVMA_WRITE);
|
|
return(1);
|
|
}
|
|
}
|
|
DEBUG_DELAY(1000000);
|
|
dvma->ctl_stat |= DVMA_FLUSH; /* self-clear */
|
|
/* disable DVMA_xfr */
|
|
dvma->ctl_stat &= ~(DVMA_ENDVMA | DVMA_WRITE);
|
|
|
|
/* see how much DVMA xfr'd */
|
|
DPRINTF2("sm_dma_cleanup: ORIG addr= %x, cnt= %x\n", h_sip->ma, req_cnt);
|
|
toutcnt = dvma->dma_addr;
|
|
DPRINTF2("sm_dma_cleanup: espstat= %x, DVMA_addr= %x\n", espstat, toutcnt);
|
|
dma_cnt = (u_short)toutcnt - (u_short)h_sip->ma;
|
|
/* see how much ESP xfr'd */
|
|
fifo_cnt = ESP_RD.fifo_flag & KEEP_5BITS;
|
|
DPRINTF2("sm_dma_cleanup: fifo_cnt= %x, dma_cnt= %x\n",
|
|
fifo_cnt, dma_cnt);
|
|
|
|
/* Figure out how much the esp chip may have xferred
|
|
* If the XZERO bit is set, we can assume that the
|
|
* ESP xferred all we asked for. */
|
|
if (espstat & ESP_STAT_XZERO)
|
|
esp_cnt = req_cnt - fifo_cnt;
|
|
else {
|
|
xfrcnt = ESP_RD.xcnt_hi << 8;
|
|
xfrcnt |= ((u_short)ESP_RD.xcnt_lo & KEEP_LBYTE);
|
|
esp_cnt = req_cnt - xfrcnt;
|
|
DPRINTF1("sm_dma_cleanup: ESP_cntr= %x\n", xfrcnt);
|
|
/* correct ESP xfr_cnt reported error */
|
|
if ((esp_cnt == 0) && (dma_cnt > 16)) {
|
|
esp_cnt = dma_cnt & (0xf);
|
|
}
|
|
esp_cnt -= fifo_cnt;
|
|
}
|
|
/* If we were sending out the scsi bus, then we believe the
|
|
* (possibly faked) transfer count register, since the esp
|
|
* chip may have prefetched to fill it's fifo. */
|
|
DPRINTF2("sm_dma_cleanup: dir= %x, espcnt= %x\n",
|
|
smsnap->sync_chk, esp_cnt);
|
|
if (smsnap->sync_chk == SM_SEND_DATA)
|
|
xfrcnt = esp_cnt;
|
|
else {
|
|
/* Else, if we were coming from the scsi bus, we only count
|
|
* that which got pumped through the dma engine. */
|
|
xfrcnt = dma_cnt;
|
|
}
|
|
DPRINTF2("sm_dma_cleanup: dir= %x, xfrcnt= %x\n",
|
|
smsnap->sync_chk, xfrcnt);
|
|
/* updated dma_count. NOTE: different from OS-> update the count */
|
|
/* to remaining bytes; while HERE = return to upper level with */
|
|
/* exact amount of bytes transferred */
|
|
h_sip->cc = xfrcnt;
|
|
#ifdef notdef
|
|
/* skip updating the addr, upper level driver might reuse the address */
|
|
/* without restoring to the original value (expecting NO change) */
|
|
h_sip->ma += xfrcnt;
|
|
#endif notdef
|
|
DPRINTF2("sm_dma_cleanup: FINAL addr= %x, cnt= %x\n",
|
|
h_sip->ma, h_sip->cc);
|
|
smsnap->sync_chk = SM_NO_DATA;
|
|
if (fifo_cnt)
|
|
ESP_WR.cmd = CMD_FLUSH;
|
|
return(ZERO);
|
|
}
|
|
|
|
/*
|
|
* Reset SCSI control logic.
|
|
*/
|
|
static int
|
|
sm_reset(h_sip, cond)
|
|
register struct host_saioreq *h_sip;
|
|
int cond;
|
|
{
|
|
register struct scsi_sm_reg *smr;
|
|
register struct udc_table *dvma;
|
|
register struct sm_snap *smsnap = &smreg_info;
|
|
register int i;
|
|
u_long toutcnt;
|
|
|
|
/* get to scsi control logic registers */
|
|
smr = (struct scsi_sm_reg *)h_sip->devaddr;
|
|
dvma = (struct udc_table *)h_sip->dmaaddr;
|
|
|
|
DPRINTF2("sm_reset: state= %x, dma_stat= %x\n",
|
|
smsnap->cur_state, dvma->ctl_stat);
|
|
DEBUG_DELAY(1000000);
|
|
if (dvma->ctl_stat & DVMA_REQPEND)
|
|
smsnap->cur_state = STATE_DVMA_STUCK;
|
|
|
|
ESP_WR.conf = ESP_CONF_DISRINT; /* disable reset INT */
|
|
|
|
/* for hard reset, cur_state must be STATE_RESET */
|
|
switch (cond) {
|
|
case RESET_EXT_ONLY:
|
|
DPRINTF("sm_reset: reset ESP/SCSI bus only\n");
|
|
ESP_WR.cmd = CMD_RESET_ESP; /* hard-reset ESP chip */
|
|
ESP_WR.cmd = CMD_NOP; /* needed for ESP bug */
|
|
ESP_WR.cmd = CMD_RESET_SCSI;
|
|
ESP_WR.cmd = CMD_NOP; /* NOP needed for ESP bug */
|
|
for (toutcnt = ZERO; toutcnt < LOOP_4SEC; toutcnt++);
|
|
i = ESP_RD.intr; /* read to clear reset interrupt */
|
|
#ifdef lint
|
|
i = i;
|
|
#endif lint
|
|
break;
|
|
case RESET_INT_ONLY:
|
|
DPRINTF("sm_reset: reset ESP only\n");
|
|
/* DVMA_EN = ZERO, INTEN=ZERO, FLUSH=1 */
|
|
dvma->ctl_stat = DVMA_FLUSH; /* soft dvma clear */
|
|
DELAY(100);
|
|
dvma->ctl_stat = ZERO; /* clear it */
|
|
/* NO ints */
|
|
ESP_WR.cmd = CMD_RESET_ESP; /* hard-reset ESP chip */
|
|
ESP_WR.cmd = CMD_NOP; /* needed for ESP bug */
|
|
break;
|
|
case RESET_ALL_SCSI:
|
|
default:
|
|
DPRINTF("sm_reset: reset DVMA/ESP/SCSI bus\n");
|
|
/* implied a reset to both ESP and SCSI bus */
|
|
dvma->ctl_stat = DVMA_RESET; /* hard DVMA reset */
|
|
DPRINTF1("sm_reset: dvma_stat= %x\n", dvma->ctl_stat);
|
|
DELAY(100);
|
|
dvma->ctl_stat = ZERO; /* clear reset */
|
|
ESP_WR.cmd = CMD_RESET_SCSI;
|
|
ESP_WR.cmd = CMD_NOP; /* NOP needed for ESP bug */
|
|
/* allow more than 2 second for scsi reset to settle */
|
|
/* Give reset scsi devices time to recover (> 2 Sec) */
|
|
for (toutcnt = ZERO; toutcnt < LOOP_4SEC; toutcnt++);
|
|
i = ESP_RD.intr; /* read to clear reset interrupt */
|
|
#ifdef lint
|
|
i = i;
|
|
#endif lint
|
|
}
|
|
/* enable parity, enable reset_int, and set host bus_id */
|
|
ESP_WR.clock_conv = DEF_CLK_CONV;
|
|
ESP_WR.timeout = DEF_TIMEOUT;
|
|
ESP_WR.sync_offset = ZERO; /* async */
|
|
#ifdef notdef
|
|
/* ignore parity enable for backward campatibilty with old shoebox */
|
|
ESP_WR.conf = ESP_CONF_PAREN | DEF_ESP_HOSTID;
|
|
#endif
|
|
ESP_WR.conf = DEF_ESP_HOSTID;
|
|
|
|
DPRINTF1("sm_reset: esp_conf= %x\n", ESP_RD.conf);
|
|
DEBUG_DELAY(1000000);
|
|
/* set up some default sm_snap */
|
|
/* "cur_err, cur_retry, and scsi_status" */
|
|
/* will be cleared in "sm_cmd() */
|
|
smsnap->cur_state = STATE_FREE;
|
|
smsnap->scsi_message = SC_COMMAND_COMPLETE;
|
|
/* dvam's ctl_stat is ZERO, which means no INTEN; */
|
|
DPRINTF1("sm_reset: done, DVMA_stat= %x\n", dvma->ctl_stat);
|
|
}
|
|
|
|
/*
|
|
* Handle a scsi interrupt.
|
|
*/
|
|
sm_intr(h_sip)
|
|
struct host_saioreq *h_sip;
|
|
{
|
|
register struct scsi_sm_reg *smr;
|
|
register struct sm_snap *smsnap = &smreg_info;
|
|
register struct udc_table *dvma;
|
|
register int i, s;
|
|
u_long toutcnt;
|
|
u_char espstat;
|
|
|
|
/* get to scsi control logic registers */
|
|
smr = (struct scsi_sm_reg *)h_sip->devaddr;
|
|
dvma = (struct udc_table *)h_sip->dmaaddr;
|
|
|
|
s = dvma->ctl_stat;
|
|
DPRINTF1("sm_intr: dma_stat: %x\n", s);
|
|
/* check dvma's req_pend, err_pend, and int_pend */
|
|
/* should only have int_pend set, if NO error */
|
|
if ((s & DVMA_INT_MASK) == ZERO) {
|
|
DPRINTF1("sm_intr: DVMA *NO* int_pend, stat: %x\n", s);
|
|
goto INTR_CHK_ERR;
|
|
}
|
|
/* Do not read ESP reg_interrupt before reading status and step reg */
|
|
/* after reading ESP reg_interrupt, ESP's INT will get cleared */
|
|
smsnap->esp_step = ESP_RD.step;
|
|
smsnap->esp_stat = ESP_RD.stat;
|
|
espstat = smsnap->esp_stat;
|
|
smsnap->esp_intr = ESP_RD.intr; /* clear INT */
|
|
DPRINTF2("sm_intr: state= %x, int= %x\n",
|
|
smsnap->cur_state, smsnap->esp_intr);
|
|
DPRINTF2("sm_intr: step= %x, stat= %x\n",
|
|
smsnap->esp_step, espstat);
|
|
|
|
if (smsnap->cur_state == STATE_DATA_REQ) {
|
|
s = dvma->ctl_stat;
|
|
DPRINTF1("sm_intr: dma_stat: %x\n", s);
|
|
smsnap->cur_retry++;
|
|
if (s & DVMA_CHK_MASK) {
|
|
if (s & DVMA_REQPEND) { /* DMA request pending */
|
|
EPRINTF1("sm_intr: DVMA-scsi req_pend, stat= %x\n", s);
|
|
/* DMA request pending, should not ocurred */
|
|
toutcnt = LOOP_4SEC; /* must be over 2sec */
|
|
/* wait for a short while to see it will clear itself */
|
|
while ((--toutcnt) && (dvma->ctl_stat & DVMA_REQPEND));
|
|
if (toutcnt == ZERO) {
|
|
smsnap->cur_err = SE_REQPEND;
|
|
goto INTR_CHK_ERR;
|
|
}
|
|
}
|
|
if (s & DVMA_ERRPEND) { /* memory exception error */
|
|
smsnap->cur_err = SE_MEMERR;
|
|
DPRINTF1("sm_intr: DVMA mem_err, stat= %x\n", s);
|
|
goto INTR_CHK_ERR;
|
|
}
|
|
}
|
|
/* status errors are mainly for internal firmware debug */
|
|
if (espstat & STAT_ERR_MASK) {
|
|
smsnap->cur_retry++;
|
|
/* ESP's status reg ERROR */
|
|
if (espstat & ESP_STAT_PERR) { /* parity error */
|
|
EPRINTF("sm_intr: SCSI bus parity error\n");
|
|
smsnap->cur_err = SE_PARITY;
|
|
}
|
|
/* if mismatch, the 'DMA" direction is wrong */
|
|
if ((((dvma->ctl_stat & DVMA_WRITE) == ZERO) &&
|
|
(smsnap->sync_chk == SM_RECV_DATA)) ||
|
|
((dvma->ctl_stat & DVMA_WRITE) &&
|
|
(smsnap->sync_chk == SM_SEND_DATA))) {
|
|
EPRINTF2("sm_intr: wrong dma dir= %x, stat= %x\n",
|
|
smsnap->sync_chk, dvma->ctl_stat);
|
|
smsnap->cur_err = SE_DIRERR;
|
|
}
|
|
if ((ESP_RD.fifo_flag & KEEP_5BITS) == MAX_FIFO_FLAG) {
|
|
/* fifo overwritten */
|
|
EPRINTF1("sm_intr: fifo_flag ERROR= %x\n",
|
|
ESP_RD.fifo_flag);
|
|
/* the 'TOP of FIFO' had been overwritten */
|
|
smsnap->cur_err = SE_FIFOVER;
|
|
}
|
|
#ifdef notdef
|
|
/* If none of the above, GROSS error is from cmd overflown */
|
|
/* top_of_cmd had been overwritten */
|
|
/* ignore this for P4-ESP for timing reason */
|
|
if (smsnap->cur_err == ZERO) {
|
|
EPRINTF1("sm_intr: cur_cmd= %x\n", ESP_RD.cmd);
|
|
smsnap->cur_err = SE_CMDOVER;
|
|
}
|
|
#endif notdef
|
|
if (smsnap->cur_err) {
|
|
EPRINTF1("sm_intr: esp stat_err= %x\n", espstat);
|
|
goto INTR_CHK_ERR;
|
|
}
|
|
}
|
|
}
|
|
|
|
INTR_CHK_STAT:
|
|
/* CORRECTON for an ESP ERRATA: ensure phase change detection reset */
|
|
ESP_WR.cmd = CMD_NOP;
|
|
smsnap->esp_stat &= ESP_PHASE_MASK;
|
|
s = ESP_RD.stat;
|
|
i = s & ESP_PHASE_MASK;
|
|
if (i != smsnap->esp_stat) {
|
|
DPRINTF2("sm_intr: phase changed, old= %x, new= %x\n",
|
|
smsnap->esp_stat, i);
|
|
smsnap->esp_stat = i;
|
|
espstat = s;
|
|
i = ESP_RD.intr;
|
|
if (i) {
|
|
DPRINTF2("sm_intr: INTR changed, old= %x, new= %x\n",
|
|
smsnap->esp_intr, i);
|
|
smsnap->esp_intr = i;
|
|
}
|
|
}
|
|
DPRINTF2("sm_intr: ESP_int= %x, state= %x\n",
|
|
smsnap->esp_intr, smsnap->cur_state);
|
|
switch (smsnap->esp_intr) {
|
|
case ESP_INT_DISCON: /* disconnect INT */
|
|
switch (smsnap->cur_state) {
|
|
/* case STATE_MSG_DISCON not needed */
|
|
case STATE_COMP_REQ: /* cmd completed seuqence sent out */
|
|
case STATE_MSG_CMPT: /* command completed msg accepted */
|
|
/* All ZERO= good, All other, bit 1= check cond, */
|
|
/* bit 3= busy, bit 4=resev conflict are errors */
|
|
if (smsnap->scsi_status & SCSI_BUSY_MASK) {
|
|
DPRINTF1("sm_intr: BUS_ERR status= %x\n",
|
|
smsnap->scsi_status);
|
|
smsnap->cur_err = SE_BUSTATERR;
|
|
}
|
|
smsnap->cur_state = STATE_FREE;
|
|
break;
|
|
case STATE_SEL_REQ: /* selection command timeout */
|
|
smsnap->cur_err = SE_SELTOUT;
|
|
case STATE_FREE:
|
|
break;
|
|
default: /* could be from target dropping BSY */
|
|
EPRINTF("sm_intr: target drop busy\n");
|
|
smsnap->cur_err = SE_PHASERR;
|
|
}
|
|
break;
|
|
case ESP_INT_FCMP:/* function complete INT */
|
|
case ESP_INT_BUS: /* from"select_seq","comp_seq","msg_accept" cmd */
|
|
case INT_OK_MASK: /* from"select_seq","comp_seq","msg_accept" cmd */
|
|
if (smsnap->cur_state == STATE_SEL_REQ) {
|
|
/* for initator, only SEL_SEQ has */
|
|
/* intermittent step indications: */
|
|
/* both sel w/wo ATN need 4 steps to complete OK */
|
|
/* only sel w/ATN/stop is 3 steps to complete OK */
|
|
/* both sel w/wo ATN need 4 steps to complete OK */
|
|
if ((smsnap->esp_step & KEEP_3BITS) != STEP_SEL_OK) {
|
|
EPRINTF2("sm_intr: BAD_SEL, step= %x, stat= %x\n",
|
|
smsnap->esp_step, smsnap->esp_stat);
|
|
if (smsnap->esp_stat != ESP_PHASE_STATUS) {
|
|
smsnap->cur_err = SE_SELTOUT;
|
|
goto INTR_CHK_ERR;
|
|
}
|
|
ESP_WR.cmd = CMD_FLUSH;
|
|
ESP_WR.cmd = CMD_NOP;
|
|
/* ready for next phase */
|
|
}
|
|
smsnap->cur_state = STATE_SEL_DONE;
|
|
}
|
|
switch (smsnap->esp_stat) { /* current phase */
|
|
case ESP_PHASE_DATA_IN: /* either data in or out */
|
|
case ESP_PHASE_DATA_OUT: /* either data in or out */
|
|
DPRINTF1("sm_intr: data phase, pre_state= %x\n",
|
|
smsnap->cur_state);
|
|
DEBUG_DELAY(1000000);
|
|
/* if this phase came after a non-command phase */
|
|
/* try to service this unexpected data phase */
|
|
if (smsnap->cur_state != STATE_SEL_DONE) {
|
|
DPRINTF("sm_intr: wrong data phase\n");
|
|
if (++smsnap->cur_retry > MAX_RETRY) {
|
|
EPRINTF("sm_intr: wrong data phase\n");
|
|
smsnap->cur_err = SE_PHASERR;
|
|
goto INTR_CHK_ERR;
|
|
}
|
|
ESP_WR.cmd = CMD_NOP;
|
|
smsnap->esp_stat = ESP_RD.stat & ESP_PHASE_MASK; i = ESP_RD.intr;
|
|
DPRINTF2("sm_intr: stat= %x, intr = %x\n",
|
|
smsnap->esp_stat, i);
|
|
if (i) {
|
|
smsnap->esp_intr = i;
|
|
goto INTR_CHK_STAT;
|
|
}
|
|
else /* just service and ignore */
|
|
goto INTR_RTN;
|
|
}
|
|
/* assume ALL cmd that has NO data, do not need DMA */
|
|
if (smsnap->sync_chk == SM_NO_DATA) {
|
|
DPRINTF1("sm_intr: spurious data phase, state= %x\n",
|
|
smsnap->cur_state);
|
|
if (++smsnap->cur_retry > MAX_RETRY) {
|
|
EPRINTF1("sm_intr: spurious data phase, state= %x\n",
|
|
smsnap->cur_state);
|
|
smsnap->cur_err = SE_PHASERR;
|
|
goto INTR_CHK_ERR;
|
|
}
|
|
/* try to fake one out a data xfr */
|
|
ESP_WR.cmd = CMD_TRAN_PAD | CMD_DMA;
|
|
}
|
|
else { /* data transfer required */
|
|
smsnap->cur_state = STATE_DATA_REQ;
|
|
/* force async transfer */
|
|
ESP_WR.sync_offset = ZERO;
|
|
/* enable dvma and R/W*/
|
|
sm_dma_setup(h_sip);
|
|
/* add in per ESP errata note */
|
|
ESP_WR.cmd = CMD_NOP;
|
|
ESP_WR.cmd = CMD_TRAN_INFO | CMD_DMA;
|
|
}
|
|
break;
|
|
case ESP_PHASE_STATUS:
|
|
DPRINTF1("sm_intr: status phase, pre_state= %x\n",
|
|
smsnap->cur_state);
|
|
if (sm_dma_cleanup(h_sip, espstat))
|
|
goto INTR_CHK_ERR;
|
|
smsnap->cur_state = STATE_COMP_REQ;
|
|
DPRINTF("sm_intr: send complete_seq\n");
|
|
ESP_WR.cmd = CMD_COMP_SEQ;
|
|
break;
|
|
case ESP_PHASE_MSG_IN:
|
|
DPRINTF2("sm_intr: msg_in phase, state= %x, flag= %x\n",
|
|
smsnap->cur_state, ESP_RD.fifo_flag);
|
|
switch (smsnap->cur_state) {
|
|
case STATE_COMP_REQ: /* two bytes */
|
|
smsnap->scsi_status = ESP_RD.fifo_data;
|
|
case STATE_MSGIN_REQ:
|
|
smsnap->scsi_message = ESP_RD.fifo_data;
|
|
break;
|
|
case STATE_DATA_REQ:
|
|
DPRINTF2("sm_intr: msg_in dma_stat= %x, cnt= %x\n",
|
|
dvma->ctl_stat, h_sip->cc);
|
|
if (sm_dma_cleanup(h_sip, espstat))
|
|
goto INTR_CHK_ERR;
|
|
/* fall through */
|
|
default:
|
|
/* get message byte */
|
|
if (ESP_RD.fifo_flag) {
|
|
if (ESP_RD.fifo_flag > 1) {
|
|
EPRINTF2("sm_intr: msg_in flag= %x, state= %x\n",
|
|
ESP_RD.fifo_flag, smsnap->cur_state);
|
|
EPRINTF2("sm_intr: stat= %x, intr= %x\n",
|
|
smsnap->esp_stat, smsnap->esp_intr);
|
|
while (ESP_RD.fifo_flag) {
|
|
i = ESP_RD.fifo_data;
|
|
EPRINTF1(" %x", i);
|
|
}
|
|
ESP_WR.cmd = CMD_NOP;
|
|
goto INTR_CHK_STAT;
|
|
}
|
|
smsnap->scsi_message = ESP_RD.fifo_data;
|
|
}
|
|
else {
|
|
ESP_WR.cmd = CMD_TRAN_INFO;
|
|
smsnap->cur_state = STATE_MSGIN_REQ;
|
|
goto INTR_RTN;
|
|
}
|
|
}
|
|
DPRINTF2("sm_intr: status= %x, message= %x\n",
|
|
smsnap->scsi_status, smsnap->scsi_message);
|
|
DPRINTF1("sm_intr: flag= %x\n", ESP_RD.fifo_flag);
|
|
switch (smsnap->scsi_message) {
|
|
case SC_COMMAND_COMPLETE:
|
|
case SC_NO_OP:
|
|
smsnap->cur_state = STATE_MSG_CMPT;
|
|
/* save the scsi_status for now */
|
|
/* a disconnect INT shuold show up */
|
|
/* after sending out "msg_accpt" cmd */
|
|
/* at that time, we are TOTALLY done */
|
|
break;
|
|
case SC_PARITY:
|
|
DPRINTF("sm_intr: PARITY_err msg\n");
|
|
smsnap->cur_err = SE_PARITY;
|
|
smsnap->cur_state = STATE_MSG_PARITY;
|
|
break;
|
|
case SC_DEVICE_RESET:
|
|
DPRINTF("sm_intr: RESET_err msg\n");
|
|
smsnap->cur_state = STATE_RESET;
|
|
smsnap->cur_err = SE_RESET;
|
|
break;
|
|
case SC_ABORT:
|
|
DPRINTF("sm_intr: ABORT_err msg\n");
|
|
smsnap->cur_state = STATE_MSG_ABORT;
|
|
smsnap->cur_err = SE_MSGERR;
|
|
break; /* no need to send abort msg */
|
|
case SC_MSG_REJECT:
|
|
DPRINTF("sm_intr: REJECT_err msg\n");
|
|
smsnap->cur_state = STATE_MSG_REJECT;
|
|
break;
|
|
/* All other is ocnsidered ERROR for now */
|
|
case SC_DISCONNECT:
|
|
case SC_SAVE_DATA_PTR:
|
|
case SC_RESTORE_PTRS:
|
|
case SC_EXTENDED_MESSAGE:
|
|
case SC_LINK_CMD_CPLT:
|
|
case SC_FLAG_LINK_CMD_CPLT:
|
|
case SC_IDENTIFY:
|
|
case SC_DR_IDENTIFY:
|
|
default:
|
|
EPRINTF1("sm_intr: unsupported message: %x\n",
|
|
smsnap->scsi_message);
|
|
smsnap->cur_err = SE_MSGERR;
|
|
}
|
|
/* send a message accpt cmd */
|
|
ESP_WR.cmd = CMD_MSG_ACPT;
|
|
ESP_WR.cmd = CMD_NOP; /* for ESP bug */
|
|
break;
|
|
case ESP_PHASE_MSG_OUT:
|
|
case ESP_PHASE_COMMAND:
|
|
default: /* all others are bad, just set PHASE error */
|
|
EPRINTF1("sm_intr: bad phase, pre_state: %x\n",
|
|
smsnap->cur_state);
|
|
smsnap->cur_err = SE_PHASERR;
|
|
}
|
|
break;
|
|
case ESP_INT_RESET: /* external scsi RESET interrupt received */
|
|
DPRINTF1("sm_intr: SCSI bus_reset int, state= %x\n",
|
|
smsnap->cur_state);
|
|
/* just set flag, and sm_reset() will be called later */
|
|
smsnap->cur_err = SE_RESET;
|
|
break;
|
|
case ESP_INT_ILLCMD: /* illegal cmd */
|
|
case INT_ILL_BUS: /* illegal bus status */
|
|
DPRINTF1("sm_intr: illegal cmd= %x\n", ESP_RD.cmd);
|
|
smsnap->cur_err = SE_ILLCMD;
|
|
break;
|
|
case ESP_INT_RESEL:
|
|
case ESP_INT_SELATN: /* selected with ATN -- target cmd */
|
|
case ESP_INT_SEL: /* selected without ATN -- target cmd */
|
|
default:
|
|
/* all others are not supported NOW */
|
|
EPRINTF1("sm_intr: bad interrupt= %x\n", smsnap->esp_intr);
|
|
smsnap->cur_err = SE_PHASERR;
|
|
}
|
|
INTR_CHK_ERR:
|
|
if (smsnap->cur_retry > MAX_RETRY) {
|
|
EPRINTF1("sm_intr: retry exhausted, phase= %x\n",
|
|
smsnap->cur_state);
|
|
DEBUG_DELAY(10000000);
|
|
smsnap->cur_err = SE_TOUTERR;
|
|
}
|
|
/* Just simply pass the status to upper level callers */
|
|
if (smsnap->cur_err) {
|
|
#ifdef SMDEBUG
|
|
if (smsnap->cur_err != SE_BUSTATERR) {
|
|
EPRINTF2("sm_intr: ESP_ERR= %x, phase= %x\n",
|
|
smsnap->cur_err, smsnap->cur_state);
|
|
}
|
|
#endif SMDEBUG
|
|
DEBUG_DELAY(1000000);
|
|
switch (smsnap->cur_err) {
|
|
case SE_SELTOUT: /* select/resel timeout */
|
|
ESP_WR.cmd = CMD_FLUSH;
|
|
ESP_WR.cmd = CMD_NOP;
|
|
break; /* return error, but NO reset */
|
|
case SE_BUSTATERR: /* bus ERR, i.e, chk_cond, busy */
|
|
smsnap->cur_err = ZERO;
|
|
smsnap->cur_state = STATE_FREE;
|
|
break; /* return error, but NO reset */
|
|
case SE_MEMERR: /* memory exception error during DMA */
|
|
case SE_DIRERR: /* WRONG DMA direction, could trash MEM */
|
|
case SE_DVMAERR: /* DVMA Drain stuck */
|
|
case SE_ILLCMD: /* illegal command detected */
|
|
case SE_PARITY: /* either ESP or target parity ERR */
|
|
case SE_FIFOVER: /* ESP status err, fifo overflown */
|
|
case SE_CMDOVER: /* ESP status err, command overflown */
|
|
case SE_RESET: /* reset detected */
|
|
/* software reset (NO external SCSI reset) */
|
|
sm_reset(h_sip, RESET_INT_ONLY);
|
|
break;
|
|
case SE_TOUTERR: /* DMA timed out */
|
|
case SE_MSGERR: /* ESP has un-expected message */
|
|
case SE_PHASERR: /* ESP has un-expected phase */
|
|
/* possible HW error, do a HARD-SCSI reset */
|
|
sm_reset(h_sip, RESET_ALL_SCSI);
|
|
break;
|
|
case SE_REQPEND: /* DMA's request pending stuck */
|
|
toutcnt = (int)dvma->ctl_stat;
|
|
EPRINTF1("sm_intr: DVMA-scsi req_pend stuck, stat= %x\n",
|
|
toutcnt);
|
|
break;
|
|
case SE_SPURINT:
|
|
EPRINTF1("sm_intr: spurious esp_intr= %x\n",
|
|
smsnap->esp_intr);
|
|
smsnap->cur_err = ZERO;
|
|
goto INTR_RTN;
|
|
default:
|
|
DPRINTF1("sm_intr: spurious esp_err= %x\n", smsnap->cur_err);
|
|
}
|
|
smsnap->cur_state = STATE_FREE;
|
|
}
|
|
INTR_RTN:
|
|
DPRINTF1("sm_intr: INTR_END, state= %x\n", smsnap->cur_state);
|
|
DEBUG_DELAY(100000);
|
|
}
|
|
#endif (defined sun4) || (defined sun3x)
|
|
|
|
/* end of SCSI-ESP standalone boot driver (smboot.c) */
|