540 lines
11 KiB
C
540 lines
11 KiB
C
/*
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* @(#)sw.c 1.1 92/07/30 Copyright (c) 1988 by Sun Microsystems, Inc.
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*/
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/*#define SWDEBUG /* Allow compiling of debug code */
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#define REL4 /* Enable release 4 mods */
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#ifdef REL4
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#include <sys/types.h>
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#include <sys/buf.h>
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#include <sun/dklabel.h>
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#include <sun/dkio.h>
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#include <stand/swreg.h>
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#include <stand/scsi.h>
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#include <stand/saio.h>
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#include <mon/sunromvec.h>
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#include <mon/idprom.h>
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#else REL4
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#include "../h/types.h"
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#include "../h/buf.h"
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#include "../sun/dklabel.h"
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#include "../sun/dkio.h"
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#include "swreg.h"
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#include "scsi.h"
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#include "saio.h"
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#include "../mon/sunromvec.h"
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#include "../mon/idprom.h"
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#endif REL4
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#ifdef SWDEBUG
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/* Handy debugging 0, 1, and 2 argument printfs */
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#define DPRINTF(str) \
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if (scsi_debug > 1) printf(str)
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#define DPRINTF1(str, arg1) \
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if (scsi_debug > 1) printf(str,arg1)
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#define DPRINTF2(str, arg1, arg2) \
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if (scsi_debug > 1) printf(str,arg1,arg2)
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/* Handy extended error reporting 0, 1, and 2 argument printfs */
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#define EPRINTF(str) \
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if (scsi_debug) printf(str)
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#define EPRINTF1(str, arg1) \
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if (scsi_debug) printf(str,arg1)
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#define EPRINTF2(str, arg1, arg2) \
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if (scsi_debug) printf(str,arg1,arg2)
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#else SWDEBUG
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#define DPRINTF(str)
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#define DPRINTF1(str, arg2)
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#define DPRINTF2(str, arg1, arg2)
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#define EPRINTF(str)
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#define EPRINTF1(str, arg2)
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#define EPRINTF2(str, arg1, arg2)
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#endif SWDEBUG
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#ifdef BOOTBLOCK
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#define SC_ERROR(str)
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#define SC_ERROR1(str, arg1)
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#else BOOTBLOCK
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#define SC_ERROR printf
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#define SC_ERROR1 printf
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#endif BOOTBLOCK
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#define SHORT_RESET 0
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#define LONG_RESET 1
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/*
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* Low-level routines common to all devices on the SCSI bus.
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*
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* Interface to the routines in this module is via a second "h_sip"
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* structure contained in the caller's local variables.
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*/
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/* How sw addresses look to the sun4/110 scsi dma hardware */
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#define SW_COBRA_DMA_ADDR(x) (((int)x)&0x00FFFFFF)
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/*
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* The interfaces we export
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*/
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extern int scsi_debug;
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extern char *devalloc();
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extern char *resalloc();
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extern int nullsys();
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extern u_char sc_cdb_size[];
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int swopen(), swdoit(), sw_reset();
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#define COBRA 1
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#define SW_COBRA_BASE 0xfa000000
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#define SW_SIZE 0x4000
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#ifdef sun4
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/*
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* Open the SCSI host adapter.
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*/
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int
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swopen(h_sip)
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register struct host_saioreq *h_sip;
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{
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register int base;
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struct idprom id;
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enum MAPTYPES space;
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DPRINTF("swopen:\n");
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/* determine type of sw interface */
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if (idprom(IDFORM_1, &id) == IDFORM_1 &&
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h_sip->ctlr == 0 &&
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id.id_machine == IDM_SUN4_COBRA) {
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EPRINTF("swopen: CPU SCSI\n");
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base = SW_COBRA_BASE;
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space = MAP_OBIO;
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} else {
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DPRINTF("swopen: failed\n");
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return (-1);
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}
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/* Map in device registers */
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h_sip->devaddr = devalloc(space, (char *)base,
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sizeof(struct scsi_sw_reg));
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if ((int)h_sip->devaddr == 0) {
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EPRINTF("swopen: devalloc failure\n");
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return (-2);
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}
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/* Allocate dma resources */
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h_sip->dmaaddr = 0;
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/* Link top level driver to host adapter */
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h_sip->doit = swdoit;
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h_sip->reset = sw_reset;
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sw_reset(h_sip, SHORT_RESET);
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return (0);
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}
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/*
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* Write a command to the SCSI bus.
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*
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* The supplied sip is the one opened by swopen().
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* DMA is done based on sip->si_ma and sip->si_cc.
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*
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* Returns -1 for error, otherwise returns the residual count not DMAed
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* (zero for success).
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*
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*/
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static int
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swdoit(cdb, scb, h_sip)
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struct scsi_cdb *cdb;
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struct scsi_scb *scb;
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register struct host_saioreq *h_sip; /* sip for host adapter */
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{
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register struct scsi_sw_reg *swr;
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register char junk;
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register u_char *cp;
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u_char size;
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register int i, b;
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DPRINTF("swdoit:\n");
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/* Get to scsi control logic registers */
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swr = (struct scsi_sw_reg *) h_sip->devaddr;
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DPRINTF1("swdoit: swr= 0x%x\n", (int)swr);
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if (sw_sbc_wait((caddr_t)&SBC_RD.cbsr, SBC_CBSR_BSY,
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SCSI_SHORT_DELAY, 0) == 0) {
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SC_ERROR("sw: bus busy\n");
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goto FAILED;
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}
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/* Select target */
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DPRINTF1("swdoit: unit= 0x%x\n", h_sip->unit);
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SBC_WR.odr = (1 << h_sip->unit) | SI_HOST_ID;
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SBC_WR.icr = SBC_ICR_DATA;
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SBC_WR.icr |= SBC_ICR_SEL;
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/* Wait for target to acknowledge our selection */
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if (sw_sbc_wait((caddr_t)&SBC_RD.cbsr, SBC_CBSR_BSY,
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SCSI_SEL_DELAY, 1) == 0) {
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EPRINTF1("sw: device offline, cbsr= 0x%x\n", SBC_RD.cbsr);
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SBC_WR.icr = 0;
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return (-2);
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}
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SBC_WR.icr = 0;
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/* Do initial dma setup */
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swr->bcr = 0; /* also reset dma_count for vme */
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if (h_sip->cc > 0) {
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if (h_sip->dma_dir == SC_RECV_DATA) {
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DPRINTF("swdoit: DMA receive\n");
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swr->csr &= ~SI_CSR_SEND;
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} else {
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DPRINTF("swdoit: DMA send\n");
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swr->csr |= SI_CSR_SEND;
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}
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}
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/* Put command onto scsi bus */
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cp = (u_char *)cdb;
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size = sc_cdb_size[CDB_GROUPID(*cp)];
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if (sw_putbyte(swr, PHASE_COMMAND, cp, size) == 0) {
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SC_ERROR("sw: cmd put failed\n");
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goto FAILED;
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}
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if (h_sip->cc > 0) {
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DPRINTF("swdoit: dma enable\n");
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/* Finish dma setup and wait for dma completion */
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if (((int)h_sip->ma & 1) || ((int)h_sip->ma & 2)) {
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SC_ERROR("sw: illegal odd dma starting address\n");
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goto FAILED;
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}
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SET_DMA_ADDR(swr, SW_COBRA_DMA_ADDR(h_sip->ma));
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SET_DMA_COUNT(swr, h_sip->cc);
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sw_dma_setup(swr, h_sip);
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/* No dma, wait for target to request a byte */
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} else if (sw_sbc_wait((caddr_t)&SBC_RD.cbsr, SBC_CBSR_REQ,
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SCSI_LONG_DELAY, 1) == 0) {
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SC_ERROR("sw: target never set REQ\n");
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goto FAILED;
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}
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/* Get status */
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junk = SBC_RD.clr;
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#ifdef lint
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junk = junk;
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#endif lint
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cp = (u_char *)scb;
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cp[0] = sw_getbyte(swr, PHASE_STATUS);
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b = sw_getbyte(swr, PHASE_MSG_IN);
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if (b != SC_COMMAND_COMPLETE) {
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EPRINTF("swdoit: no cmd complete msg\n");
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/* If b < 0, sw_getbyte already printed msg */
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if (b >= 0)
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SC_ERROR("sw: invalid message\n");
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goto FAILED;
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}
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/* Compute number of bytes actually transferred. */
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if (h_sip->cc == 0)
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return (0);
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i = SW_COBRA_DMA_ADDR(swr->dma_addr | 0xFF000000);
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return ( (int)(i - SW_COBRA_DMA_ADDR(h_sip->ma)) );
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FAILED:
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EPRINTF("swdoit: failed\n");
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sw_reset(h_sip, LONG_RESET);
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return (-1);
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}
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static int
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sw_dma_setup(swr, h_sip)
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register struct scsi_sw_reg *swr;
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register struct host_saioreq *h_sip;
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{
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register char junk;
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register char *cp;
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DPRINTF("sw_dma_setup:\n");
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/* setup sbc and start dma */
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SBC_WR.mr |= SBC_MR_DMA;
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if (h_sip->dma_dir == SC_RECV_DATA) {
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SBC_WR.tcr = TCR_DATA_IN;
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SBC_WR.ircv = 0;
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} else {
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SBC_WR.tcr = TCR_DATA_OUT;
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SBC_WR.icr = SBC_ICR_DATA;
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SBC_WR.send = 0;
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}
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swr->csr |= SI_CSR_DMA_EN;
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/* wait for dma completion */
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if (sw_wait(&swr->csr,
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SI_CSR_SBC_IP | SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR, 1) == 0) {
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SC_ERROR("sw: dma never completed\n");
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swr->csr &= ~SI_CSR_DMA_EN;
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sw_dma_cleanup(swr);
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goto FAILED;
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}
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/* check reason for dma completion */
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if (swr->csr & SI_CSR_SBC_IP) {
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/* dma operation should end with a phase mismatch */
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swr->csr &= ~SI_CSR_DMA_EN;
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(void) sw_sbc_wait((caddr_t)&SBC_RD.bsr, SBC_BSR_PMTCH,
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SCSI_SHORT_DELAY, 0);
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} else {
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swr->csr &= ~SI_CSR_DMA_EN;
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if (swr->csr & SI_CSR_DMA_CONFLICT) {
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SC_ERROR("sw: illegal reg access during dma\n");
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} else if (swr->csr & SI_CSR_DMA_BUS_ERR) {
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SC_ERROR("sw: bus error during dma\n");
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} else {
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SC_ERROR("sw: dma overrun\n");
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}
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sw_dma_cleanup(swr);
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goto FAILED;
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}
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/* handle special dma recv situations */
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if (h_sip->dma_dir == SC_RECV_DATA) {
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cp = (char *)((swr->dma_addr&0xFFFFFC) | 0xff000000);
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switch (swr->dma_addr & 0x3) {
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case 3:
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*cp = (swr->bpr & 0xff000000) >> 24;
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*(cp + 1) = (swr->bpr & 0x00ff0000) >> 16;
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*(cp + 2) = (swr->bpr & 0x0000ff00) >> 8;
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break;
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case 2:
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*cp = (swr->bpr & 0xff000000) >> 24;
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*(cp + 1) = (swr->bpr & 0x00ff0000) >> 16;
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break;
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case 1:
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*cp = (swr->bpr & 0xff000000) >> 24;
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break;
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}
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}
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/* clear sbc interrupt */
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junk = SBC_RD.clr;
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#ifdef lint
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junk = junk;
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#endif lint
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/* Cleanup after a dma operation */
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sw_dma_cleanup(swr);
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FAILED:
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return;
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}
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/*
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* Reset some register information after a dma operation.
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*/
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static int
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sw_dma_cleanup(swr)
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register struct scsi_sw_reg *swr;
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{
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DPRINTF("sw_dma_cleanup:\n");
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swr->csr &= ~SI_CSR_DMA_EN;
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SBC_WR.mr &= ~SBC_MR_DMA;
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SBC_WR.icr = 0;
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SBC_WR.tcr = 0;
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}
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/*
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* Wait for a condition to be (de)asserted.
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*/
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static int
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sw_wait(reg, cond, set)
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register u_int *reg;
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register u_int cond;
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register int set;
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{
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register int i;
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register u_int regval;
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for (i = 0; i < SCSI_LONG_DELAY; i++) {
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regval = *reg;
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if ((set == 1) && (regval & cond)) {
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return (1);
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}
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if ((set == 0) && !(regval & cond)) {
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return (1);
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}
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DELAY(10);
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}
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return (0);
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}
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/*
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* Wait for a condition to be (de)asserted on the scsi bus.
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*/
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static int
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sw_sbc_wait(reg, cond, delay, set)
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register caddr_t reg;
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register u_char cond;
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register int delay;
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register int set;
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{
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register int i;
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register u_char regval;
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DPRINTF("sw_sbc_wait:\n");
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for (i = 0; i < delay; i++) {
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regval = *reg;
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if ((set == 1) && (regval & cond)) {
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return (1);
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}
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if ((set == 0) && !(regval & cond)) {
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return (1);
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}
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DELAY(10);
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}
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return (0);
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}
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/*
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* Put a byte onto the scsi bus.
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*/
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static int
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sw_putbyte(swr, phase, data, num)
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register struct scsi_sw_reg *swr;
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register u_short phase;
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register u_char *data;
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register u_char num;
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{
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register int i;
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u_char icr;
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DPRINTF("sw_putbyte:\n");
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/* Set up tcr so a phase match will occur */
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swr->sbc_wreg.tcr = phase >> 2;
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icr = SBC_WR.icr;
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/* Put all desired bytes onto scsi bus */
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for (i = 0; i < num; i++) {
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SBC_WR.icr = icr | SBC_ICR_DATA; /* clear ack */
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/* Wait for target to request a byte */
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if (sw_sbc_wait((caddr_t)&SBC_RD.cbsr, SBC_CBSR_REQ,
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SCSI_SHORT_DELAY, 1) == 0) {
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SC_ERROR1("sw: REQ not active, cbsr 0x%x\n",
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SBC_RD.cbsr);
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return (0);
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}
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/* Load data for transfer */
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SBC_WR.odr = *data++;
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/* Complete req/ack handshake */
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SBC_WR.icr |= SBC_ICR_ACK;
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if (sw_sbc_wait((caddr_t)&SBC_RD.cbsr, SBC_CBSR_REQ,
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SCSI_SHORT_DELAY, 0) == 0) {
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SC_ERROR("sw: target never released REQ\n");
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return (0);
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}
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}
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SBC_WR.tcr = 0;
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SBC_WR.icr = 0;
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return (1);
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}
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/*
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* Get a byte from the scsi bus.
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*/
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static int
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sw_getbyte(swr, phase)
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register struct scsi_sw_reg *swr;
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register u_short phase;
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{
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register u_char data;
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DPRINTF("sw_getbyte:\n");
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/* Wait for target request */
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if (sw_sbc_wait((caddr_t)&SBC_RD.cbsr, SBC_CBSR_REQ,
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SCSI_SHORT_DELAY, 1) == 0) {
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SC_ERROR1("sw: REQ not active, cbsr 0x%x\n",
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SBC_RD.cbsr);
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SBC_WR.tcr = 0;
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return (-1);
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}
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/* Check for correct phase on scsi bus */
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if (phase != (SBC_RD.cbsr & CBSR_PHASE_BITS)) {
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SC_ERROR1("sw: wrong phase, cbsr 0x%x\n",
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SBC_RD.cbsr);
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return (-1);
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}
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/* Grab data */
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data = SBC_RD.cdr;
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SBC_WR.icr = SBC_ICR_ACK;
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/* Complete req/ack handshake */
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if (sw_sbc_wait((caddr_t)&SBC_RD.cbsr, SBC_CBSR_REQ,
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SCSI_SHORT_DELAY, 0) == 0) {
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SC_ERROR("sw: target never released REQ\n");
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SBC_WR.icr = 0;
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return (-1);
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}
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SBC_WR.icr = 0; /* Clear ack */
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return (data);
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}
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/*
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* Reset SCSI control logic.
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*/
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static int
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sw_reset(h_sip, flag)
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register struct host_saioreq *h_sip;
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int flag;
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{
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register struct scsi_sw_reg *swr;
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register char junk;
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EPRINTF("sw_reset:\n");
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swr = (struct scsi_sw_reg *) h_sip->devaddr;
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/* Reset bcr, fifo, udc, and sbc */
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swr->csr = 0;
|
|
DELAY(10);
|
|
swr->csr = SI_CSR_SCSI_RES | SI_CSR_FIFO_RES;
|
|
SET_DMA_ADDR(swr, 0);
|
|
SET_DMA_COUNT(swr, 0);
|
|
|
|
/* Issue scsi bus reset */
|
|
if (flag != SHORT_RESET) {
|
|
SBC_WR.icr = SBC_ICR_RST;
|
|
DELAY(100);
|
|
SBC_WR.icr = 0;
|
|
SBC_WR.tcr = 0;
|
|
SBC_WR.mr = 0;
|
|
junk = SBC_RD.clr;
|
|
#ifdef lint
|
|
junk = junk;
|
|
#endif lint
|
|
DELAY(SCSI_RESET_DELAY); /* Recovery time */
|
|
}
|
|
}
|
|
#endif sun4
|