467 lines
16 KiB
C
467 lines
16 KiB
C
/*
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* @(#) dbri_reg.h 1.1@(#) Copyright (c) 1991-92 Sun Microsystems, Inc.
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*/
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/*
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* DBRI - Dual Basic Rate ISDN
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*/
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#ifndef _sbusdev_dbrireg_h
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#define _sbusdev_dbrireg_h
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typedef union {
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unsigned int fcode_i[12]; /* Forth header available after reset */
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unsigned short fcode_s[24];
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unsigned char fcode_c[48];
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} dbri_fcode_t;
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typedef union {
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struct { /* ATT register definitions (r) */
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unsigned int
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reg0, /* Reg0 (64) - Status Register */
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reg1, /* Reg1 (68) - Mode and Interrupt Register */
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reg2, /* Reg2 (72) - Parallel Input/Output */
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reg3, /* Reg3 (76) - Test Mode */
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:32, :32, :32, :32,
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reg8, /* Reg8 (96) - Program Counter */
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reg9; /* Reg9 (100) - Interrupt Queue Pointer */
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} r;
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struct { /* mneumonic structure of registers (n) */
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unsigned int
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sts, /* Reg0 (64) - Status Register */
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intr, /* Reg1 (68) - Mode and Interrupt Register */
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pio, /* Reg2 (72) - Parallel Input/Output */
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tst_mode, /* Reg3 (76) - Test Mode */
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:32, :32, :32, :32,
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cmdqp, /* Reg8 (96) - Program Counter */
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intrqp; /* Reg9 (100) - Interrupt Queue Pointer */
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} n;
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} dbri_reg_t;
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/*
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* (sts_reg0) Status register (Register 0) defines
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*/
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#define DBRI_STS_PIPEOFFSET 16 /* bit offset for pipe 0 */
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#define DBRI_STS_P (1 << 15) /* Queue Pointer Valid */
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#define DBRI_STS_S (1 << 13) /* 16-Word SBus Burst */
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#define DBRI_STS_E (1 << 12) /* 8-Word SBus Burst */
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#define DBRI_STS_G (1 << 14) /* 4-Word SBus Burst */
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#define DBRI_STS_X (1 << 7) /* Sanity Timer Disable */
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#define DBRI_STS_T (1 << 6) /* Enable TE Interface */
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#define DBRI_STS_N (1 << 5) /* Enable NT Interface */
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#define DBRI_STS_C (1 << 4) /* Enable CHI Interface */
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#define DBRI_STS_F (1 << 3) /* Force Sanity Timer Timeout */
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#define DBRI_STS_D (1 << 2) /* Disable SBus Master Mode */
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#define DBRI_STS_H (1 << 1) /* Halt for Analysis */
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#define DBRI_STS_R (1 << 0) /* Soft Reset */
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/*
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* (intr_reg1) Mode and Interrupt register (Register 1) defines
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*/
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#define DBRI_INTR_LIT_ENDIAN (1 << 8) /* Little Endian Byte Order */
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#define DBRI_INTR_MRR_ERR (1 << 4) /* Multiple Error Ack on SBus */
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#define DBRI_INTR_LATE_ERR (1 << 3) /* Multiple Late Err on SBus */
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#define DBRI_INTR_BUS_GRANT_ERR (1 << 2) /* Lost Bus Grant on SBus */
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#define DBRI_INTR_BURST_ERR (1 << 1) /* Multiple Burst Err on SBus */
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#define DBRI_INTR_REQ (1 << 0) /* Interrupt Request */
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/*
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* (pio_reg2) Parallel Input Output register (Register 2) defines
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*/
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#define DBRI_PIO_0 (1 << 0) /* PDN */
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#define DBRI_PIO_1 (1 << 1) /* RESET */
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#define DBRI_PIO_2 (1 << 2) /* Internal PDN */
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#define DBRI_PIO_3 (1 << 3) /* Data/Control Mode */
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#define DBRI_PIO0_EN (1 << 4) /* Parallel I/O Enable lines */
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#define DBRI_PIO1_EN (1 << 5)
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#define DBRI_PIO2_EN (1 << 6)
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#define DBRI_PIO3_EN (1 << 7)
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/*
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* (tst_mode_reg3) Test Mode register (Register 3) defines
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*/
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#define DBRI_TST_MODE_SPEED (1 << 2) /* High Speed Test Mode */
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#define DBRI_TST_MODE_PIO (1 << 3) /* PIO inputs replace receivers */
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/* Command Set */
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#define DBRI_OPSHIFT (28)
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#define DBRI_OP(x) (((unsigned)x)>>DBRI_OPSHIFT)
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#define DBRI_CMD_WAIT (0x0 << DBRI_OPSHIFT) /* Wait */
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#define DBRI_CMD_PAUSE (0x1 << DBRI_OPSHIFT) /* Pause */
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#define DBRI_CMD_JMP (0x2 << DBRI_OPSHIFT) /* Jump to new command queue */
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#define DBRI_CMD_JMP_LEN (2)
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#define DBRI_CMD_IIQ (0x3 << DBRI_OPSHIFT) /* Initialize interrupt queue */
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#define DBRI_CMD_REX (0x4 << DBRI_OPSHIFT) /* Report cmd via interrupt */
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#define DBRI_CMD_SDP (0x5 << DBRI_OPSHIFT) /* Set-up data pipe */
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#define DBRI_CMD_CDP (0x6 << DBRI_OPSHIFT) /* Continue data pipe */
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#define DBRI_CMD_DTS (0x7 << DBRI_OPSHIFT) /* Define time slot */
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#define DBRI_OPCODE_DTS 0x7 /* DTS command for bit fields */
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#define DBRI_CMD_SSP (0x8 << DBRI_OPSHIFT) /* Set short pipe data */
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#define DBRI_CMD_CHI (0x9 << DBRI_OPSHIFT) /* Set CHI global mode */
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#define DBRI_CMD_NT (0xa << DBRI_OPSHIFT) /* NT command */
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#define DBRI_CMD_TE (0xb << DBRI_OPSHIFT) /* TE command */
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#define DBRI_CMD_CDEC (0xc << DBRI_OPSHIFT) /* Codec setup */
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#define DBRI_CMD_TEST (0xd << DBRI_OPSHIFT) /* Test */
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#define DBRI_CMD_CDM (0xe << DBRI_OPSHIFT) /* CHI data mode */
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/* These apply to multiple commands */
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#define DBRI_CMDI (1 << 27) /* Interrupt on cmd complete */
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#define DBRI_CMD_VALUE(a) (a & 0x07ff) /* Command tag value */
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#define DBRI_CMD_MASK (0xf << DBRI_OPSHIFT) /* Command mask value */
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/* Set-up Data Pipe (SDP) Command bit defines */
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#define DBRI_SDP_IRM (1 << 18) /* Enables UNDR, RBYT intrs */
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#define DBRI_SDP_PIPE(a) (a & 0x1f) /* Pipe number */
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/* IRM for Fixed data change interrupt (FXDT) */
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#define DBRI_SDP_TWOSAME (1 << 18) /* 2nd time value received */
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#define DBRI_SDP_CHNG (2 << 18) /* report data change */
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#define DBRI_SDP_ALLVAL (3 << 18) /* report all values */
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#define DBRI_SDP_EOL (1 << 17) /* End of List intr enable */
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#define DBRI_SDP_IBEG (1 << 16) /* Masks IBEG and IEND intrs */
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#define DBRI_SDP_TRANSPARENT (0 << 13) /* Transparent mode */
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#define DBRI_SDP_HDLC (2 << 13) /* HDLC mode */
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#define DBRI_SDP_TE_DCHNL (3 << 13) /* HDLC TE D Channel mode */
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#define DBRI_SDP_SERIAL (4 << 13) /* Serial in to out (no DMA) */
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#define DBRI_SDP_FIXED (6 << 13) /* Fixed Data (also no DMA) */
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#define DBRI_SDP_MODEMASK (7 << 13) /* Mask for SDP mode */
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#define DBRI_SDP_D (1 << 12) /* Transmit direction */
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#define DBRI_SDP_B (1 << 11) /* MSBit transmitted first */
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#define DBRI_SDP_PTR (1 << 10) /* Use ptr for new TD/RD */
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#define DBRI_SDP_IDL (1 << 9) /* Send idle following frame */
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#define DBRI_SDP_ABT (1 << 8) /* Set abort in data FIFO */
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#define DBRI_SDP_CLR (1 << 7) /* Clear pipe */
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#define DBRI_SDP_CMDMASK (0xf << 7)
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/* Continue Data Pipe (CDP) Command bit defines */
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#define DBRI_CDP_PIPE(a) (a & 0x1f) /* Pipe number */
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/* Define Time Slot (DTS) Command structures */
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union dbri_dtscmd {
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struct {
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unsigned
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cmd:4, /* DTS command */
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cmdi:1, /* command intr bit */
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res:9, /* reserved */
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vi:1, /* valid input tsd */
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vo:1, /* valid output tsd */
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id:1, /* insert/delete bit */
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oldin:5, /* old input pipe */
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oldout:5, /* old output pipe */
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pipe:5; /* current pipe */
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} r;
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unsigned int word32;
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};
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/*
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* Note that the r structure can be used for almost all transactions in
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* the driver as this is the common case for regular xmit and recv pipe
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* setup. For the chi the special "chi" structure should be used. This
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* struct is good enough for both xmit and receive chi modes.
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*/
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union dbri_dtstsd {
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struct {
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unsigned
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len:8, /* length */
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cycle:10, /* cycle */
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di:1, /* data invert */
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mode:3, /* mode */
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mon:5, /* monitor pipe */
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next:5; /* next pipe */
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} r;
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struct {
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unsigned
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:19,
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mode:3, /* mode */
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:5, /* monitor pipe */
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next:5; /* next pipe */
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} chi;
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unsigned int word32;
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};
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/* Define Time Slot (DTS) Command bit defines */
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#define DBRI_DTS_VI 1 /* Valid Input TSD */
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#define DBRI_DTS_VO 1 /* Valid Output TSD */
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#define DBRI_DTS_ID 1 /* Add/Modify time slot */
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#define DBRI_DTS_DI 1 /* Data Invert */
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#define DBRI_DTS_SINGLE 0 /* Single channel */
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#define DBRI_DTS_MONITOR 2 /* Monitor receive pipe (tee) */
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#define DBRI_DTS_INDIRECT 3 /* Indirect for multi TS */
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#define DBRI_DTS_ALTERNATE 7 /* Alternate coding */
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/* Set Short Pipe (SSP) Command bit defines */
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#define DBRI_SSP_PIPE(a) (a & 0x1f) /* Pipe number */
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/* Set CHI Global Mode (CHI) Command bit defines */
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#define DBRI_CHI_CHICM(a) ((a & 0xff) << 16) /* CHI clock mode */
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#define DBRI_CHI_INT (1 << 15) /* Intr and reporting mask */
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#define DBRI_CHI_CHIL (1 << 14) /* Lost frame sync intr */
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#define DBRI_CHI_OD (1 << 13) /* Open Drain */
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#define DBRI_CHI_FE (1 << 12) /* Frame edge high */
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#define DBRI_CHI_FD (1 << 11) /* Frame drive on rising edge */
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#define DBRI_CHI_BPF(a) (a & 0x7ff) /* CHI bits per frame */
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/* NT and TE Command bit defines */
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#define DBRI_NTE_IRM_STATUS (1 << 15) /* IRM - force immed intr */
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#define DBRI_NTE_IRM_SBRI (1 << 14) /* IRM - Enable SBRI intrs */
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#define DBRI_NTE_ISNT (1 << 13) /* NT when set, TE otherwise */
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#define DBRI_NT_FT (1 << 12) /* Fixed timing */
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#define DBRI_NTE_EZ (1 << 11) /* Send zeros in E channel */
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#define DBRI_NTE_IFA (1 << 10) /*
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* Inhibit final
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* activation (A bit)
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*/
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#define DBRI_NTE_ACT (1 << 9) /* Activate interface */
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#define DBRI_NT_MFE (1 << 8) /* Multiframe enable */
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#define DBRI_TE_QE (1 << 8) /* Q channel enable */
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#define DBRI_NTE_RLB_D (1 << 7) /* Remote loop back D chnl */
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#define DBRI_NTE_RLB_B1 (1 << 6) /* Remote loop back B1 chnl */
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#define DBRI_NTE_RLB_B2 (1 << 5) /* Remote loop back B2 chnl */
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#define DBRI_NTE_LLB_D (1 << 4) /* Local loop back D chnl */
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#define DBRI_NTE_LLB_B1 (1 << 3) /* Local loop back B1 chnl */
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#define DBRI_NTE_LLB_B2 (1 << 2) /* Local loop back B2 chnl */
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#define DBRI_NTE_FACT (1 << 1) /* Force Immediate Activation */
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#define DBRI_NTE_ABV (1 << 0) /* Add. BiPolar Violation Det */
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/* Codec Setup (CDEC) Command bit defines */
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#define DBRI_CDEC_DISABL_CLK (0 << 24) /* Disable CKCOD (high) */
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#define DBRI_CDEC_2MHZ (1 << 24) /* 2.048 MHz CKCOD */
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#define DBRI_CDEC_1_5MHZ (2 << 24) /* 1.536 MHz CKCOD */
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#define DBRI_CDEC_FE_FSCOD(a) ((a & 0x7ff) << 12) /* Falling edge delay */
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#define DBRI_CDEC_RE_FSCOD(a) (a & 0x7ff) /* Rising edge delay */
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/* Test Command bit defines */
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#define DBRI_TST_RAMPTR(a) ((a && 3ff) << 16) /* RAM pointer */
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#define DBRI_TST_SIZE(a) ((a && 1f) << 11) /* Size field */
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#define DBRI_TST_ROMMON 0x5 /* ROM monitor toggle */
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#define DBRI_TST_SBUS 0x6 /* SBus test/copy */
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#define DBRI_TST_SERIAL 0x7 /* Serial Controller test */
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#define DBRI_TST_RAM_RD 0x8 /* RAM read */
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#define DBRI_TST_RAM_WT 0x9 /* RAM write */
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#define DBRI_TST_RAM_BIST 0xa /* RAM Built in Self-Test */
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#define DBRI_TST_UCTL_BIST 0xb /* Ucontroller BIST */
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#define DBRI_TST_ROM_DUMP 0xc /* ROM dump */
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/* Set CHI Data Mode Command */
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#define DBRI_CDM_THI (1 << 8) /* Transmit data on CHIDR */
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#define DBRI_CDM_RHI (1 << 7) /* Receive data from CHIDX */
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#define DBRI_CDM_RCE (1 << 6) /* Receive clock rising edge */
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#define DBRI_CDM_CMSR (1 << 5) /* Clock mode 2 pulse select */
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#define DBRI_CDM_ODD (1 << 4) /* Strobe on odd clock count */
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#define DBRI_CDM_CMSX (1 << 3) /* Two clocks per bit */
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#define DBRI_CDM_XCE (1 << 2) /* Transmit on rising edge */
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#define DBRI_CDM_XEN (1 << 1) /* Transmit enable */
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#define DBRI_CDM_REN (1 << 0) /* Receive enable */
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/* structure of DBRI commands */
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typedef struct dbri_chip_cmd {
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unsigned cmd_wd1;
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unsigned cmd_wd2; /* data, pointer, or input tsd */
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unsigned cmd_wd3; /* pointer or output tsd */
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} dbri_chip_cmd_t;
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struct dbri_code_sbri { /* SBRI */
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unsigned int
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:12,
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:9,
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vta:1, /* voltage threshold adjustment */
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berr:1, /* detectible bit error */
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ferr:1, /* frame sync error */
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mfm:1, /* multi-frame mode */
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fsc:1, /* frame sync established */
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rif4:1, /* if TE A-bit is set */
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rif0:1, /* no signal received */
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act:1, /* command bit 9 (activate) */
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tss:3; /* interface activation state */
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};
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struct dbri_code_chil { /* CHIL */
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unsigned int
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:12,
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:16,
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overflow:1, /* CHI receiver overflow */
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nofs:1, /* Ext frame sync not detected 250Us */
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xact:1, /* CHI transmitter active */
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ract:1; /* CHI receiver active */
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};
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typedef union {
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struct {
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unsigned int
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ibits:2, /* I bits */
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channel:6, /* channel number */
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code:4, /* interrupt code */
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field:20; /* interrupt field */
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} f;
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struct { /* CMDI */
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unsigned int
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:12,
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opcode:4, /* opcode of command */
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value:16; /* value field of command */
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} code_cmdi;
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struct dbri_code_sbri code_sbri;
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struct { /* FXDT */
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unsigned int
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:12,
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changed_data:20;
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} code_fxdt;
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struct dbri_code_chil code_chil;
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unsigned int word32;
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} dbri_intrq_ent_t;
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#define DBRI_MAX_QWORDS 63 /* Max # of intr queue words */
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/* DBRI interrupt queue structure */
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typedef struct dbri_intq {
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struct dbri_intq *nextq; /* next interrupt queue ptr */
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dbri_intrq_ent_t intr[DBRI_MAX_QWORDS]; /* intr queue words */
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} dbri_intq_t;
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/* Interrupt ibit bits */
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#define DBRI_INT_IBITS 0x2 /* Set on intr in queue structure */
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/* Interrupt channel bits */
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#define DBRI_INT_MAX_CHNL (32) /* Maximum pipe channel number */
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#define DBRI_INT_TE_CHNL (32) /* TE channel interrupt status */
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#define DBRI_INT_NT_CHNL (34) /* NT channel interrupt status */
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#define DBRI_INT_CHI_CHNL (36) /* CHI channel interrupt status */
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#define DBRI_INT_REPORT_CHNL (38) /* Report Command channel intr status */
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#define DBRI_INT_OTHER_CHNL (40) /* Other channel interrupt status */
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/* Interrupt code bits */
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#define DBRI_INT_BRDY 0x1 /* Buffer ready for processing */
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#define DBRI_INT_MINT 0x2 /* Marked interrupt in RD/TD */
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#define DBRI_INT_IBEG 0x3 /* Flag to idle transition detected */
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#define DBRI_INT_IEND 0x4 /* Idle to flag transition detected */
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#define DBRI_INT_EOL 0x5 /* End of list */
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#define DBRI_INT_CMDI 0x6 /* 1st word of command read by DBRI */
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#define DBRI_INT_XCMP 0x8 /* Transmission of frame complete */
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#define DBRI_INT_SBRI 0x9 /* BRI status change INFO */
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#define DBRI_INT_FXDT 0xa /* Fixed data change */
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#define DBRI_INT_CHIL 0xb /* CHI lost frame sync */
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#define DBRI_INT_COLL 0xb /* Unrecoverable D-channel collision */
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#define DBRI_INT_DBYT 0xc /* Dropped byte frame slip */
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#define DBRI_INT_RBYT 0xd /* Repeated byte frame slip */
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#define DBRI_INT_LINT 0xe /* Lost interrupt */
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#define DBRI_INT_UNDR 0xf /* DMA underrun */
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/* SBRI tss bit field definitions */
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#define DBRI_NTINFO0_G1 0x0 /* Inactive and NOT TRYING to act */
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#define DBRI_NTINFO2_G2 0x6 /* Sending framing */
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#define DBRI_NTINFO4_G3 0x7 /* Sending data */
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#define DBRI_NTINFO0_G4 0x1 /* Use illegal code for State G4 */
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#define DBRI_TEINFO0_F1 0x0 /* Inactive and NOT TRYING to act */
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#define DBRI_TEINFO0_F8 0x2 /* Lost framing */
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#define DBRI_TEINFO0_F3 0x3 /* Not seeking activation */
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#define DBRI_TEINFO1_F4 0x4 /* Sending request for activation */
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#define DBRI_TEINFO0_F5 0x5 /* Requested act but no framing yet */
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#define DBRI_TEINFO3_F6 0x6 /* Sending framing */
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#define DBRI_TEINFO3_F7 0x7 /* Sending data */
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/* DBRI transmit message descriptor structure */
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typedef union dbri_tmd {
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struct {
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unsigned int
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eof:1, /* End of frame */
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dcrc:1, /* Do not append CRC */
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:1,
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cnt:13, /* Data byte count */
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fint:1, /* Frame interrupt */
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mint:1, /* Mark interrupt */
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idl:1, /* Transmit idle characters */
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fcnt:13; /* Flag fill count */
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unsigned char *bufp; /* buffer pointer */
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union dbri_tmd *fp; /* forward descriptor pointer */
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unsigned int status; /* status */
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} f; /* access as named fields */
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unsigned int word32[4]; /* access as 32 bit words for diags */
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} dbri_tmd_t;
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/*
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* ISDN Priority Class for D-Channel Access method.
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* (CCITT Fascicle III.8, 6.1.4)
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*/
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#define DBRI_D_CLASS_1 0 /* D-channel call control priority */
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#define DBRI_D_CLASS_2 1 /* D-channel normal priority */
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/* xmit descriptor status bits */
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#define DBRI_TMD_UNR (1 << 3) /* Underrun */
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#define DBRI_TMD_ABT (1 << 2) /* Abort */
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#define DBRI_TMD_TFC (1 << 1) /* Transmit frame complete */
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#define DBRI_TMD_TBC (1 << 0) /* Transmit buffer complete */
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/* DBRI receive message descriptor structure */
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typedef union dbri_rmd {
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struct {
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unsigned int
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eof:1, /* End of frame */
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com:1, /* Buffer complete */
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:1,
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cnt:13, /* Data byte count */
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:8,
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status:8; /* Status */
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unsigned char *bufp; /* buffer pointer */
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union dbri_rmd *fp; /* forward descriptor pointer */
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unsigned int
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:16,
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fint:1, /* Frame interrupt */
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mint:1, /* Mark interrupt */
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:1,
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bcnt:13; /* Buffer count */
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} f; /* access as named fields */
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unsigned int word32[4]; /* access as 32 bit words for diags */
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} dbri_rmd_t;
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/* DBRI's DMA engine can handle a maximum size of 8191 bytes per frame
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* on both transmit and receive.
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*/
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#define DBRI_MAXPACKET (8191)
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/* receive message descriptor status bits */
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#define DBRI_RMD_CRC (1 << 7) /* CRC status */
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#define DBRI_RMD_BBC (1 << 6) /* Bad byte count */
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#define DBRI_RMD_ABT (1 << 5) /* Abort */
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#define DBRI_RMD_OVRN (1 << 3) /* Overrun condition detected */
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#endif /* !_sbusdev_dbri_reg_h */
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