255 lines
6.6 KiB
C
255 lines
6.6 KiB
C
/* @(#)reg.h 1.1 92/07/30 SMI */
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/*
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* Copyright (c) 1985 by Sun Microsystems, Inc.
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*/
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#ifndef _sparc_reg_h
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#define _sparc_reg_h
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/*
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* Location of the users' stored
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* registers relative to R0.
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* Usage is u.u_ar0[XX].
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*/
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#define PSR (0)
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#define PC (1)
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#define nPC (2)
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#define Y (3)
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#define G1 (4)
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#define G2 (5)
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#define G3 (6)
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#define G4 (7)
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#define G5 (8)
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#define G6 (9)
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#define G7 (10)
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#define O0 (11)
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#define O1 (12)
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#define O2 (13)
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#define O3 (14)
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#define O4 (15)
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#define O5 (16)
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#define O6 (17)
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#define O7 (18)
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/* the following defines are for portability */
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#define PS PSR
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#define SP O6
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#define R0 O0
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#define R1 O1
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/*
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* And now for something completely the same...
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*/
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#ifndef LOCORE
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struct regs {
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int r_psr; /* processor status register */
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int r_pc; /* program counter */
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int r_npc; /* next program counter */
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int r_y; /* the y register */
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int r_g1; /* user global regs */
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int r_g2;
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int r_g3;
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int r_g4;
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int r_g5;
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int r_g6;
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int r_g7;
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int r_o0;
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int r_o1;
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int r_o2;
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int r_o3;
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int r_o4;
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int r_o5;
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int r_o6;
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int r_o7;
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};
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#define r_ps r_psr /* for portablility */
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#define r_r0 r_o0
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#define r_sp r_o6
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#endif !LOCORE
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/*
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* Floating point definitions.
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*/
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#define FPU /* we have an external float unit */
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#ifndef LOCORE
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#define FQ_DEPTH 16 /* maximum instuctions in FQ */
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/*
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* struct fp_status is the floating point processor state
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* struct fpu is the sum total of all possible floating point state
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* which includes the state of external floating point hardware,
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* fpa registers, etc..., if it exists.
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*/
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struct fpq {
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unsigned long *addr; /* address */
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unsigned long instr; /* instruction */
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};
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struct fq {
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union { /* FPU inst/addr queue */
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double whole;
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struct fpq fpq;
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} FQu;
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};
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#define FPU_REGS_TYPE unsigned
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#define FPU_FSR_TYPE unsigned
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struct fp_status {
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union { /* FPU floating point regs */
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FPU_REGS_TYPE Fpu_regs[32]; /* 32 singles */
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double Fpu_dregs[16]; /* 16 doubles */
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} fpu_fr;
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FPU_FSR_TYPE Fpu_fsr; /* FPU status register */
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unsigned Fpu_flags; /* control flags */
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unsigned Fpu_extra; /* extra word */
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unsigned Fpu_qcnt; /* count of valid entries in fps_q */
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struct fq Fpu_q[FQ_DEPTH]; /* FPU instruction address queue */
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};
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#define fpu_regs f_fpstatus.fpu_fr.Fpu_regs
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#define fpu_dregs f_fpstatus.fpu_fr.Fpu_dregs
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#define fpu_fsr f_fpstatus.Fpu_fsr
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#define fpu_flags f_fpstatus.Fpu_flags
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#define fpu_extra f_fpstatus.Fpu_extra
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#define fpu_q f_fpstatus.Fpu_q
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#define fpu_qcnt f_fpstatus.Fpu_qcnt
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struct fpu {
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struct fp_status f_fpstatus;
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};
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#endif !LOCORE
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/*
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* Definition of bits in the Sun-4 FSR (Floating-point Status Register)
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* ________________________________________________________________________
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* | RD | RP | TEM | NS | res | vers | FTT | QNE | PR | FCC | AEXC | CEXC |
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* |-----|---- |-----|----|-----|------|-----|-----|----|-----|------|------|
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* 31 30 29 28 27 23 22 21 20 19 17 16 14 13 12 11 10 9 5 4 0
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*/
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#define FSR_CEXC 0x0000001f /* Current Exception */
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#define FSR_AEXC 0x000003e0 /* ieee accrued exceptions */
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#define FSR_FCC 0x00000c00 /* Floating-point Condition Codes */
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#define FSR_PR 0x00001000 /* Partial Remainder */
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#define FSR_QNE 0x00002000 /* Queue not empty */
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#define FSR_FTT 0x0001c000 /* Floating-point Trap Type */
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#define FSR_VERS 0x000e0000 /* version field */
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#define FSR_RESV 0x00300000 /* reserved */
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#define FSR_NS 0x00400000 /* non-standard fp */
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#define FSR_TEM 0x0f800000 /* ieee Trap Enable Mask */
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#define FSR_RP 0x30000000 /* Rounding Precision */
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#define FSR_RD 0xc0000000 /* Rounding Direction */
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#define FSR_VERS_SHIFT (17) /* amount to shift version field */
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/*
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* Definition of CEXC (Current EXCeption) bit field of fsr
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*/
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#define FSR_CEXC_NX 0x00000001 /* inexact */
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#define FSR_CEXC_DZ 0x00000002 /* divide-by-zero */
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#define FSR_CEXC_UF 0x00000004 /* underflow */.
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#define FSR_CEXC_OF 0x00000008 /* overflow */
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#define FSR_CEXC_NV 0x00000010 /* invalid */
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/*
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* Definition of AEXC (Accrued EXCeption) bit field of fsr
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*/
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#define FSR_AEXC_NX (0x1 << 5) /* inexact */
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#define FSR_AEXC_DZ (0x2 << 5) /* divide-by-zero */
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#define FSR_AEXC_UF (0x4 << 5) /* underflow */.
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#define FSR_AEXC_OF (0x8 << 5) /* overflow */
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#define FSR_AEXC_NV (0x10 << 5) /* invalid */
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/*
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* Defintion of FTT (Floating-point Trap Type) field within the FSR
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*/
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#define FTT_NONE 0 /* no excepitons */
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#define FTT_IEEE 1 /* IEEE exception */
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#define FTT_UNFIN 2 /* unfinished fpop */
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#define FTT_UNIMP 3 /* unimplemented fpop */
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#define FTT_SEQ 4 /* sequence error */
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#define FTT_ALIGN 5 /* alignment, by software convention */
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#define FTT_DFAULT 6 /* data fault, by software convention */
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#define FSR_FTT_SHIFT 14 /* shift needed to justfy ftt field */
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#define FSR_FTT_IEEE (FTT_IEEE << FSR_FTT_SHIFT)
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#define FSR_FTT_UNFIN (FTT_UNFIN << FSR_FTT_SHIFT)
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#define FSR_FTT_UNIMP (FTT_UNIMP << FSR_FTT_SHIFT)
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#define FSR_FTT_SEQ (FTT_SEQ << FSR_FTT_SHIFT)
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#define FSR_FTT_ALIGN (FTT_ALIGN << FSR_FTT_SHIFT)
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#define FSR_FTT_DFAULT (FTT_DFAULT << FSR_FTT_SHIFT)
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/*
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* Values of VERS (version) field within the FSR
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* NOTE: these values are overloaded; the cpu type must be used to
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* further discriminate amongst these. For that reason, no #defines are
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* provided.
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*
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* Version cpu = 21-22, 51-54 cpu = 23-24, 55-57
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* 0 Weitek 1164/5 (FAB 1-4) TI 8847
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* 1 Weitek 1164/5 (FAB 5-6) LSI L64814
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* 2 TI 8847 TI TMS390C602A
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* 3 Weitek 3170 Weitek 3171
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* 4 Meiko ?
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* 5 ? ?
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* 6 ? ?
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* 7 No FP Hardware No FP Hardware
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*/
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/*
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* Definition of TEM (Trap Enable Mask) bit field of fsr
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*/
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#define FSR_TEM_NX (0x1 << 23) /* inexact */
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#define FSR_TEM_DZ (0x2 << 23) /* divide-by-zero */
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#define FSR_TEM_UF (0x4 << 23) /* underflow */.
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#define FSR_TEM_OF (0x8 << 23) /* overflow */
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#define FSR_TEM_NV (0x10 << 23) /* invalid */
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/*
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* Definition of RP (Rounding Precision) field of fsr
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*/
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#define RP_DBLEXT 0 /* double-extended */
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#define RP_SINGLE 1 /* single */
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#define RP_DOUBLE 2 /* double */
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#define RP_RESERVED 3 /* unused and reserved */
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/*
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* Defintion of RD (Rounding Direction) field of fsr
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*/
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#define RD_NEAR 0 /* nearest or even if tie */
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#define RD_ZER0 1 /* to zero */
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#define RD_POSINF 2 /* positive infinity */
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#define RD_NEGINF 3 /* negative infinity */
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/*
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* Definition of the FP enable flags of the pcb struct
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* Normal operation, all flags are zero
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*/
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#define FP_UNINITIALIZED 1
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#define FP_STARTSIG 2
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#define FP_DISABLE 4
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#define FP_ENABLE 8
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#ifndef LOCORE
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/*
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* How a register window looks on the stack.
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*/
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struct rwindow {
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int rw_local[8]; /* locals */
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int rw_in[8]; /* ins */
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};
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#define rw_fp rw_in[6] /* frame pointer */
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#define rw_rtn rw_in[7] /* return address */
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#endif !LOCORE
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#endif /*!_sparc_reg_h*/
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