252 lines
10 KiB
C
252 lines
10 KiB
C
/*
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* cpu.map.h
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*
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* @(#)cpu.map.h 1.1 92/07/30 Copyr 1986 Sun Micro
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* Copyright (c) 1986 by Sun Microsystems, Inc.
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*/
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/*
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* Memory Mapping and Paging on the Sun-3
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*
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* This file is used for both standalone code (ROM Monitor,
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* Diagnostics, boot programs, etc) and for the Unix kernel. IF YOU HAVE
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* TO CHANGE IT to fit your application, MOVE THE CHANGE BACK TO THE PUBLIC
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* COPY, and make sure the change is upward-compatible. The last thing we
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* need is seventeen different copies of this file, like we have with the
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* Sun-1 header files.
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*/
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#ifndef ADRSPC_SIZE
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/*
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* The address space available to a single process is 256 Megabytes.
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*/
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#define ADRSPC_SIZE 0x10000000
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/*
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* The context register selects among 8 different address spaces. Each
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* address space typically corresponds to a process and is 256 megabytes.
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* Each memory access is translated thru the address space indicated by
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* the context register.
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*
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* The context register occupies a byte in control space, although only
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* the low 3 bits are relevant. The high-order bits are ignored on writes,
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* and return garbage on reads. You can mask with CONTEXTMASK.
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*/
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typedef unsigned char context_t;
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#define NUMCONTEXTS 8
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#define CONTEXTMASK (NUMCONTEXTS-1) /* Relevant bits on read of cx reg */
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/*
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* The segment map determines which large pieces of the 256MB address space
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* are actually in use. Each chunk of address space is mapped to a set of
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* PGSPERSEG page map entries. Chunks which are not in use should all be
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* mapped to a single set of page map entries, which should prohibit
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* all accesses.
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*
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* There are SEGSPERCONTEXT segment map entries in each logical context.
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* There are NUMPMEGS total page map entry groups (pmegs) in the physical
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* page map. Each segment map entry references a pmeg which contains
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* the PGSPERSEG pages defining that segment.
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*
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* Note that there is much more virtual address space (256M) as there
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* is physical space mappable at one time (8M). You can't map in 256 megs
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* at once even if you have that much physical memory, since the page map
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* is the bottleneck here. The solution is to "page" the page map entries
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* in and out of the physical pmegs on demand.
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*/
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typedef unsigned char segnum_t; /* Segment number */
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#define SEGSPERCONTEXT 2048
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#define NUMPMEGS 256
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#define PGSPERSEG 16
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/*
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* The following are valid in the pm_type field of the page map.
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*/
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enum pm_types {
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VPM_MEMORY = 0, /* Page is in main memory */
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VPM_IO = 1, /* Page is onboard I/O */
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VPM_VME16 = 2, /* Page is on VMEbus, accessing 16-bit dev */
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VPM_VME32 = 3, /* Page is on VMEbus, accessing 32-bit dev */
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VPM_MEMORY_NOCACHE = 4, /* Page is in main memory, but not cacheable */
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};
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/*
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* The following are valid in the pm_permissions field.
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*/
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enum pm_perm {
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PMP_RO = 0, /* Page is read-only by all */
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PMP_RO_SUP = 1, /* Page is read-only by supervisor */
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PMP_ALL = 2, /* Page is read-write by all */
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PMP_SUP = 3, /* Page is read-write by supervisor */
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};
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/*
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* The page map gives fine-grain control over memory allocation. Each page
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* map entry controls BYTESPERPG (a page) of memory. Each page can be mapped
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* to memory, I/O, or a global bus (eg, VMEbus), or can be inaccessible.
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* Each page can be protected against user access and can be made readable
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* or read/write. If access is denied, the
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* page referenced and modified bits will not be changed, nor will the page
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* number or type fields be used; so they can be used by software.
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*/
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#define BYTESPERPG 8192
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#define BYTES_PG_SHIFT 13
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struct pgmapent {
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unsigned pm_valid :1; /* This entry is valid */
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enum pm_perm pm_permissions :2; /* Access privileges */
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enum pm_types pm_type :3; /* Type of page+don't cache */
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unsigned pm_accessed :1; /* Page has been read */
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unsigned pm_modified :1; /* Page has been written */
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unsigned pm_reserved :5; /* served */
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unsigned pm_page :19; /* Page # in physical memory */
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};
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#define PMREALBITS 0xFF07FFFF /* Which are actually implemented */
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#define PMREALBITS_M25 0xFF0007FF /* Which for M25 */
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/*
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* When the page type is PM_IO, the page number field selects
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* which of the main I/O device chips is being selected. Low-order (non-
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* mapped) address bits connect to the address lines of the device and
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* determine which facility of the device is being accessed.
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*/
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#define VIOPG_KBM 0x00 /* Dual serial Z8530 SCC for keyboard&mouse */
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#define VIOPG_SERIAL0 0x10 /* Dual serial Z8530 SCC */
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#define VIOPG_EEPROM 0x20 /* Non-volatile memory */
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#define VIOPG_CLOCK 0x30 /* Intersil 7170 time-of-day clock */
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#define VIOPG_MEMORY_ERR 0x40 /* Uncorrectable Memory Error registers */
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#define VIOPG_INTERRUPT 0x50 /* Interrupt control register */
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#define VIOPG_ETHER 0x60 /* Intel 82586 Ethernet interface */
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#define VIOPG_COLORMAP 0x70 /* Color Map for onboard video, PRISM */
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#define VIOPG_PROM 0x80 /* Bootstrap proms */
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#define VIOPG_AMD_ETHER 0x90 /* AMD Ethernet interface */
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#define VIOPG_SCSI 0xA0 /* Onboard SCSI interface */
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/* 0xB0 /* Reserved */
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/* 0xC0 /* Reserved */
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/* 0xD0 /* Reserved */
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#define VIOPG_DES 0xE0 /* AMD 8068 data ciphering processor */
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#define VIOPG_ECC_CTRL 0xF0 /* ECC Control Register access */
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/*
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* Other special page numbers.
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*/
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#ifdef PRISM
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/* these are the physical page numbers */
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#define MEMPG_VIDEO (0xFF000000 >> BYTES_PG_SHIFT) /* prism bw frame buf */
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#define MEMPG_BW_ENABLE (0xFE400000 >> BYTES_PG_SHIFT) /* enable plane */
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#define MEMPG_PRISM_CFB (0xFE800000 >> BYTES_PG_SHIFT) /* prism color fb */
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#endif PRISM
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#ifdef SUN3F
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#define MEMPG_VIDEO (0xFF000000 >> BYTES_PG_SHIFT) /* sun3f bw frame buf */
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#define MEMPG_RES (0xFF1C0000 >> BYTES_PG_SHIFT) /* hi/low res switch */
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#define MEMPG_P4_REG (0xFF300000 >> BYTES_PG_SHIFT) /* P4 bus register */
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#define MEMPG_OVERLAY (0xFF400000 >> BYTES_PG_SHIFT) /* overlay plane */
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#define MEMPG_BW_ENABLE (0xFF600000 >> BYTES_PG_SHIFT) /* enable plane */
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#define MEMPG_PRISM_CFB (0xFF800000 >> BYTES_PG_SHIFT) /* prism color fb */
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#define MEMPG_SUN3F_CFB (0xFF800000 >> BYTES_PG_SHIFT) /* sun3f color fb */
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#define MEMPG_COLORMAP (0xFF200000 >> BYTES_PG_SHIFT) /* sun3f colormap */
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#define MEMPG_P4_MFB1 (0xFF400000 >> BYTES_PG_SHIFT) /* P4 mono FB 1 */
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#define MEMPG_P4_MFB2 (0xFF600000 >> BYTES_PG_SHIFT) /* P4 mono FB 2 */
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#define MEMPG_P4_CMAP1 (0xFF200000 >> BYTES_PG_SHIFT) /* P4 color map 1 */
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#define MEMPG_P4_OVRLAY1 (0xFF400000 >> BYTES_PG_SHIFT) /* P4 overlay pl 1 */
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#define MEMPG_P4_ENABLE1 (0xFF600000 >> BYTES_PG_SHIFT) /* P4 enable pl 1 */
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#define MEMPG_P4_CFB1 (0xFF800000 >> BYTES_PG_SHIFT) /* P4 color FB 1 */
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#endif SUN3F
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#ifdef CARRERA
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#define MEMPG_VIDEO (0xFF000000 >> BYTES_PG_SHIFT) /* carrera frame buf */
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#endif CARRERA
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#ifdef SIRIUS
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#define MEMPG_VIDEO (0xFF000000 >> BYTES_PG_SHIFT) /* carrera frame buf */
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#endif SIRIUS
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#ifdef M25
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#define MEMPG_VIDEO (0x00100000 >> BYTES_PG_SHIFT) /* FB in main mem */
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#endif M25
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#define VMEPG_24ADDR (0xFF000000 >> BYTES_PG_SHIFT) /* 24-bit addr VME */
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#define VMEPG_16ADDR (0xFFFF0000 >> BYTES_PG_SHIFT) /* 16-bit addr VME */
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#define VME_COLOR_PHYS 0xFF400000 /* Base addr (not pg#) of VME color */
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#define VPM_VME_COLOR VPM_VME16 /* Page type for VME color */
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#define VMEPG_COLOR (VME_COLOR_PHYS >> BYTES_PG_SHIFT)
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#if defined(PRISM) || defined(SUN3F)
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#define MONBEG MONSTART-PRISM_CFB_SIZE
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#else
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#define MONBEG MONSTART
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#endif PRISM || SUN3F
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/*
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* The maps are accessed from supervisor state by using the "movs" (Move
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* Spacey) instruction. This moves a byte, word, or longword to/from a
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* register and a location in another address space. The Sun-3 hardware
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* defines one of these address spaces (defined by function code values)
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* as the "control address space", including various control registers
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* as well as the maps. The particular map accessed is determined
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* by the high-order 4 bits of the address used. The particular entry accessed
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* is determined by the middle-order bits of the address used --
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* we access the entry that controls that page. Which particular byte(s) of
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* the map entry are accessed is controlled by the low-order bits of the
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* address used, as usual.
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*
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* The following defines the encodings for the various address spaces used
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* by "movs".
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*/
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#define FC_UD 1 /* User Data */
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#define FC_UP 2 /* User Program */
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#define FC_MAP 3 /* Sun-3 Memory Maps */
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#define FC_SD 5 /* Supervisor Data */
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#define FC_SP 6 /* Supervisor Program */
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#define FC_CPU 7 /* CPU Space (Int Ack, Co-processors, ...) */
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#define SEGMAPADR(addr) (char *)(((int)addr&MAPADDRMASK)+SMAPOFF)
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#define PAGEMAPADR(addr)(long *)(((int)addr&MAPADDRMASK)+PMAPOFF)
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#define IDPROMOFF 0x00000000 /* ID Prom */
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#define PMAPOFF 0x10000000 /* Page map offset within maps */
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#define SMAPOFF 0x20000000 /* Segment map offset within maps */
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#define CONTEXTOFF 0x30000000 /* Context registers */
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#define ENABLEOFF 0x40000000 /* System Enable Reg -- turns me on */
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#define UDMAENABLEOFF 0x50000000 /* User DVMA Enable Reg */
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#define BUSERROFF 0x60000000 /* Bus Error Register - tells why */
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#define LEDOFF 0x70000000 /* LED's for diagnostics -- 0=lit */
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#define SERIALOFF 0xF0000000 /* Serial port bypass for diagnostics */
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#define MAPADDRMASK 0x0FFFE000 /* Keeps bits relevant to map entry */
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/*
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* The following subroutines accept any address in the mappable range
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* (256 megs). They access the map for the current context. They
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* assume that we are currently running in supervisor state.
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*
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* We can't declare getpgmap() as returning a struct, because our C compiler
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* is brain damaged and returns a pointer to a static area if you return a
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* struct. We therefore return an int and require the caller to set up
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* unions and other assorted random hacks because the language
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* implementation doesn't support structures returned from reentrant routines.
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*/
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extern /*struct pgmapent*/ getpgmap(); /* (addr) */
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extern setpgmap(); /* (addr, entry) */
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extern segnum_t getsegmap(); /* (addr) */
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extern setsegmap(); /* (addr, entry) */
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extern context_t getsupcontext(); /* () */
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extern setsupcontext(); /* (entry) */
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extern context_t getusercontext(); /* () */
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extern setusercontext(); /* (entry) */
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#endif ADRSPC_SIZE
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