35 lines
1.0 KiB
C
35 lines
1.0 KiB
C
/* @(#)interreg.h 1.1 92/07/30 SMI */
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/*
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* Copyright (c) 1985 by Sun Microsystems, Inc.
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*/
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/*
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* The interrupt register provides for the generation of software
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* interrupts and controls the video and clock hardware interrupts.
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*/
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#ifndef _sun3_interreg_h
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#define _sun3_interreg_h
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#define OBIO_INTERREG 0xA0000 /* address of interreg in obio space */
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#ifdef LOCORE
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#define INTERREG 0x0FFE6000 /* virtual address we map interreg to be at */
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#else
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#define INTERREG ((u_char *)(0x0FFE6000))
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#endif
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/*
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* Bits of the interrupt register.
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*/
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#define IR_ENA_CLK7 0x80 /* r/w - enable clock level 7 interrupt */
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#define IR_ENA_CLK5 0x20 /* r/w - enable clock level 5 interrupt */
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#define IR_ENA_VID4 0x10 /* r/w - enable video level 4 interrupt */
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#define IR_SOFT_INT3 0x08 /* r/w - cause software level 3 interrupt */
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#define IR_SOFT_INT2 0x04 /* r/w - cause software level 2 interrupt */
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#define IR_SOFT_INT1 0x02 /* r/w - cause software level 1 interrupt */
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#define IR_ENA_INT 0x01 /* r/w - enable (all) interrupts */
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#endif /*!_sun3_interreg_h*/
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