78 lines
3.1 KiB
C
78 lines
3.1 KiB
C
/* @(#)memerr.h 1.1 92/07/30 SMI */
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/*
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* Copyright (c) 1986 by Sun Microsystems, Inc.
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*/
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/*
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* All Sun-3 implementations have either memory parity error detection
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* or memory equipped with error correction (ECC). The memory error
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* register consists of a control and an address register. If an error
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* occurs, the control register stores information relevant to the error.
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* The memory address error register stores the virtual address, the
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* context number, and the CPU/DVMA bit of the memory cycle at which
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* the error was detected. Errors are reported via a non-maskable
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* level 7 interrupt. In case of multiple (stacked) memory errors,
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* the information relation to the first error is latched in the
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* memory error register. The interrupt is held pending and the error
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* information in the memory error register is latched (frozen) until
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* it is cleared (unfrozen) by a write to bits <31..24> of the memory
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* error address register.
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*/
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#ifndef _sun3_memerr_h
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#define _sun3_memerr_h
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#define OBIO_MEMREG 0x80000 /* address of memreg in obio space */
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#ifdef LOCORE
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#define MEMREG 0x0FFE4000 /* virtual address we map memreg to be at */
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#else
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struct memreg {
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u_char mr_er; /* memory error control register */
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#define mr_per mr_er /* parity error register */
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#define mr_eer mr_er /* ECC error register */
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u_char mr_undef[3];
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u_int mr_dvma : 1;
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u_int mr_ctx : 3;
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u_int mr_vaddr:28;
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};
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#define MEMREG ((struct memreg *)(0x0FFE4000))
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#endif LOCORE
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/*
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* Bits for the memory error register when used as parity error register
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*/
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#define PER_INTR 0x80 /* r/o - 1 = parity interrupt pending */
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#define PER_INTENA 0x40 /* r/w - 1 = enable interrupt on parity error */
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#define PER_TEST 0x20 /* r/w - 1 = write inverse parity */
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#define PER_CHECK 0x10 /* r/w - 1 = enable parity checking */
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#define PER_ERR24 0x08 /* r/o - 1 = parity error <24..31> */
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#define PER_ERR16 0x04 /* r/o - 1 = parity error <16..23> */
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#define PER_ERR08 0x02 /* r/o - 1 = parity error <8..15> */
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#define PER_ERR00 0x01 /* r/o - 1 = parity error <0..7> */
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#define PER_ERR 0x0F /* r/o - mask for some parity error occuring */
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#define PARERR_BITS "\20\10INTR\7INTENA\6TEST\5CHECK\4ERR24\3ERR16\2ERR08\1ERR00"
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/*
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* Bits for the memory error register when used as ECC error register
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*/
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#define EER_INTR 0x80 /* r/o - ECC memory interrupt pending */
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#define EER_INTENA 0x40 /* r/w - enable interrupts on errors */
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#define EER_BUSHOLD 0x20 /* r/w - hold memory bus mastership */
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#define EER_CE_ENA 0x10 /* r/w - enable CE recording */
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#define EER_TIMEOUT 0x08 /* r/o - Sirius bus time out */
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#define EER_WBACKERR 0x04 /* r/o - write back error */
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#define EER_UE 0x02 /* r/o - UE, uncorrectable error */
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#define EER_CE 0x01 /* r/o - CE, correctable (single bit) error */
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#define EER_ERR 0x0F /* r/o - mask for some ECC error occuring */
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#define ECCERR_BITS "\20\10INTR\7INTENA\6BUSHOLD\5CE_ENA\4TIMEOUT\3WBACKERR\2UE\1CE"
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#define ER_INTR 0x80 /* mask for ECC/parity interrupt pending */
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#define ER_INTENA 0x40 /* mask for ECC/parity enable interrupt */
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#define MEMINTVL 60 /* sixty second delay for softecc */
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#endif /*!_sun3_memerr_h*/
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