54 lines
1.7 KiB
C
54 lines
1.7 KiB
C
/* @(#)psl.h 1.1 92/07/30 SMI */
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/*
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* Copyright (c) 1987, 1988, 1989 by Sun Microsystems, Inc.
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*/
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/*
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* Definition of bits in the 68020 status register (SR)
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* We always use the 68020 interrupt stack because the
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* pain of fixing up the master stack when returning
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* off the interrupt stack is too high.
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*/
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#ifndef _sun3_psl_h
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#define _sun3_psl_h
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#define SR_T1 0x8000 /* trace on any intruction */
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#define SR_T0 0x4000 /* trace on change flow */
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#define SR_SMODE 0x2000 /* system mode */
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#define SR_MASTER 0x1000 /* master mode (non-interrupt) */
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#define SR_INTPRI 0x0700 /* interrupt priority bits */
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#define SR_CC 0x001F /* all condition code bits */
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/* Handy values for SR */
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#define SR_HIGH 0x2700 /* supervisor (interrupt) high pri */
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#define SR_LOW 0x2000 /* supervisor (interrupt) low pri */
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#define SR_USER 0x0000 /* user, low priority */
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#define SR_USERCLR 0xFF00 /* system bits */
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#define SR_TRACE SR_T1 /* trace mode mask - use T1 (any) */
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#define PSL_USER SR_USER /* must set for user */
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#define PSL_USERMASK ~SR_USERCLR /* must clear for user */
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#define PSL_ALLCC SR_CC /* condition code bits */
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#define PSL_T SR_TRACE /* trace bit */
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/* convert a interrupt priority to a spl (SR) cookie */
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#define ipltospl(n) (SR_SMODE|((n)<<8))
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/* convert a system prority level to a spl (SR) cookie */
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#define pritospl(n) ipltospl(n)
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/* convert an spl (SR) cookie back to either a level or interrupt priority */
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#define spltopri(n) (((n) & SR_INTPRI) >> 8)
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#define spltoipl(n) spltopri(n)
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/*
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* Note that on the sun3, interrupt priority and system priority are
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* identical. On other architectures this is not necessarily the case.
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*/
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#endif /*!_sun3_psl_h*/
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