139 lines
3.7 KiB
C
139 lines
3.7 KiB
C
/* @(#)mmu.h 1.1 92/07/30 SMI */
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/*
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* Copyright (c) 1987 by Sun Microsystems, Inc.
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*/
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/*
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* Sun-3x memory management.
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* This file gives more mmu specific constants.
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*/
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#ifndef _sun3x_mmu_h
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#define _sun3x_mmu_h
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#include <machine/devaddr.h>
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#include <machine/iocache.h> /* for 4.1 driver source compatibility */
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/*
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* Process address space is 32 bits
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*/
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#define ADDRESS_MASK 0xffffffff /* Mask of valid bits of an address */
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/*
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* Page table information.
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*/
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#define MMU_L3_SHIFT MMU_PAGESHIFT /* level 3 table shift */
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#define MMU_L3_MASK 0x0007e000 /* address bits in table */
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#define MMU_L2_SHIFT (MMU_L3_SHIFT + 6) /* level 2 table shift */
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#define MMU_L2_MASK 0x01f80000 /* address bits in table */
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#define MMU_L1_SHIFT (MMU_L2_SHIFT + 6) /* level 1 table shift */
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#define MMU_L1_MASK 0xfe000000 /* address bits in table */
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#define NL3PTEPERPT 64 /* entries in table */
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#define NL3PTESHIFT 6 /* log 2 of above */
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#define L3PTSIZE (NL3PTEPERPT * MMU_PAGESIZE) /* bytes mapped */
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#define L3PTOFFSET (L3PTSIZE - 1)
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#define NL2PTEPERPT 64 /* entries in table */
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#define L2PTSIZE (NL2PTEPERPT * L3PTSIZE) /* bytes mapped */
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#define L2PTOFFSET (L2PTSIZE - 1)
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#define NL1PTEPERPT 128 /* entries in table */
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/*
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* Values for invalid page table entries. We use defines instead of
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* structures so that the startup code can use these even when it's
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* running at the wrong addresses.
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*/
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#define MMU_INVALIDPTE 0
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#define MMU_INVALIDSPTP 0
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#define MMU_INVALIDLPTP1 0x7FFFFC00
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#define MMU_INVALIDLPTP2 0
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/*
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* 68030 code register values.
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*/
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#define FC_UD 1 /* user data */
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#define FC_UP 2 /* user program */
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/*
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* we must use fc 4 rather than 3 as in sun3 for bcopy because the 68030 mmu
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* treats fc 3 accesses as in user mode
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*/
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#define FC_MAP 4 /* Sun-3x bcopy hardware */
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#define FC_SD 5 /* supervisor data */
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#define FC_SP 6 /* supervisor program */
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#define FC_CPU 7 /* cpu space */
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/*
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* Various devices.
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*/
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#define ID_PROM (V_IDPROM_ADDR)
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#define ID_EEPROM (V_EEPROM_ADDR+0x7d8)
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#define IDPROMSIZE 0x20
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#define IOMAP_SIZE 0x2000
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/*
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* 68030 Cache Control Register
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*/
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#define ICACHE_BURST 0x0010
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#define ICACHE_ENABLE 0x0001 + ICACHE_BURST
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#define ICACHE_FREEZE 0x0002
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#define ICACHE_CLRENTRY 0x0004
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#define ICACHE_CLEAR 0x0008
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#ifndef NO_DCACHE
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#define DCACHE_BURST 0x1000
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#define DCACHE_ENABLE 0x2100 + DCACHE_BURST
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#define DCACHE_FREEZE 0x0200
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#define DCACHE_CLRENTRY 0x0400
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#define DCACHE_CLEAR 0x0800
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#else
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/* no data cache */
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#define DCACHE_ENABLE 0
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#define DCACHE_FREEZE 0
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#define DCACHE_CLRENTRY 0
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#define DCACHE_CLEAR 0
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#endif
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/*
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* 68030 MMU Status Register
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*/
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#define MMU_BERR 0x8000 /* bus error */
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#define MMU_LIMIT 0x4000 /* limit violation */
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#define MMU_SUPER 0x2000 /* supervisor violation */
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#define MMU_WPROT 0x0800 /* write protected */
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#define MMU_INVLD 0x0400 /* invalid entry */
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#define MMU_MOD 0x0200 /* modified bit */
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#define MMU_TRANS 0x0040 /* transparent bit */
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#define MMU_LEVEL 0x0007 /* table level */
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/*
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* Error types for mmu faults
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*/
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#define MMUE_INVALID 0x01 /* invalid error */
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#define MMUE_SUPER 0x02 /* access violation */
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#define MMUE_PROTERR 0x03 /* write protect error */
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/*
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* Block Copy Read and Block Copy Write. Because we have a 32 bit virtual
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* address, the masks don't actually do anything.
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*/
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#define BC_LINESIZE 16
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#define BC_LINE_SHIFT 2
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#define BC_LINE_RESIDU 3
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#define BC_BLOCK_CPCMD 0x00000000
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#define BC_BLOCK_OFF 0xffffffff
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#if defined(KERNEL) && !defined(LOCORE)
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/*
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* Cache specific routines. These include routines for the data cache
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* and the translation cache.
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*/
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void vac_flush();
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void atc_flush_all();
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void atc_flush_entry(/* addr */);
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#endif defined(KERNEL) && !defined(LOCORE)
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#endif /*!_sun3x_mmu_h*/
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