213 lines
6.9 KiB
C
213 lines
6.9 KiB
C
/* @(#)eccreg.h 1.1 92/07/30 SMI */
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/*
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* Copyright (c) 1987 by Sun Microsystems, Inc.
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*/
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#ifndef _sun4_eccreg_h
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#define _sun4_eccreg_h
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#define OBIO_ECCREG0_ADDR 0xFF1E0000 /* addr in obio space - sunrise */
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#define OBIO_ECCREG1_ADDR 0xFF000000 /* addr in obio space - sunray */
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#define MAX_ECC 6 /* max number of ECC memory cards */
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#define ECCREG_ADDR (MDEVBASE + 0x4000) /* virtual address mapped to */
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#ifdef LOCORE
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#define ECCREG ECCREG_ADDR
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#else
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#define ECCREG ((union eccreg *)ECCREG_ADDR)
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union eccreg {
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struct sirius {
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u_int ena;
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u_int syn;
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u_int dreg1;
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u_int dreg2;
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u_char pad[64 - (4 * sizeof (u_int))];
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} ecc_s;
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struct moonshine {
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u_int ena;
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u_int err;
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u_int syn;
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u_char pad0[32 - (3 * sizeof (u_int))];
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u_int dreg1;
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u_int dreg2;
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u_char pad1[32 - (2 * sizeof (u_int))];
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} ecc_m;
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};
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#endif /* LOCORE */
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/*
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* since access to memory board registers is limited
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* to a particular sized operation, we define a bunch of masks
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*/
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/* sirius ecc memory enable register */
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/* <31..29>, r/o - board type identifier */
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#define ENA_TYPE_MASK 0xE0000000
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#define TYPE0 0x0
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/* <28, 27>, r/w - operation mode */
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#define ENA_MODE_MASK 0x18000000
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#define ENA_MODE_NORMAL 0
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#define ENA_MODE_DIAG_GENERATE 0x08000000
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#define ENA_MODE_DIAG_DETECT 0x10000000
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#define ENA_MODE_DIAG_INIT 0x18000000
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/* <26..25>, r/o - board size */
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#define ENA_BDSIZE_MASK 0x06000000
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#define ENA_BDSIZE_4MB 0
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#define ENA_BDSIZE_8MB 0x02000000
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#define ENA_BDSIZE_16MB 0x04000000
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#define ENA_BDSIZE_32MB 0x06000000
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/* <24>, r/w - enable refresh scrub cycle */
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#define ENA_SCRUB_MASK 0x01000000
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/* <23>, r/w - enable mem bus ecc reporting */
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#define ENA_BUSENA_MASK 0x00800000
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/* <22>, r/w - overall board enable */
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#define ENA_BOARDENA_MASK 0x00400000
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/* <21..16>, r/w - base address <A27..A22> */
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#define ENA_ADDR_MASK 0x003F0000
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/* <21..15>, r/w - base address <A29..A23> */
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#define ENA_ADDR_MASKL 0x003F8000
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/* left logical shift to become <A27..A22> */
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#define ENA_ADDR_SHIFT (22-16)
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/* left logical shift to become <A29..A24> */
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#define ENA_ADDR_SHIFTL (23-16)
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/* <14> r/w P2.CANCEL enable */
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#define ENA_CANCEL 0x00004000
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/* <13> r/w 1 GB Enable */
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#define ENA_1GB 0x00002000
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/* <12..0>, non-exist */
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/* syndrome */
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/* <31..24>, r/o - syndrome for first error */
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#define SY_SYND_MASK 0xFF000000
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/* right shift to printf in %b format */
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#define SY_SYND_SHIFT 24
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/* <23>, reserved, read as 0 */
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/* <22..1>, r/o - real addr bits <A24..A3> */
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#define SY_ADDR_MASK 0x007FFFFE
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/* left logical shift to become <24..A3> */
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#define SY_ADDR_SHIFT (3-1)
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/* <0>, r/o - correctable error */
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#define SY_CE_MASK 0x00000001
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/* eccdiag_reg1 */
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/* <31..24>, w/o - don' care */
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/* <23>, w/o - check bit 32 (data D<71>) */
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#define DR_CB32_MASK 0x00800000
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/* <22..7>, w/o - don't care */
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/* <6>, w/o - check bit 16 (data D<70>) */
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#define DR_CB16_MASK 0x00000040
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/* <5..0>, w/o - don't care */
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/* eccdiag_reg2 */
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/* <31..6>, w/o - don't care */
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/* <5>, w/o - check bit 8 (data D<69>) */
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#define DR_CB8_MASK 0x00000020
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/* <4>, w/o - check bit 4 (data D<68>) */
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#define DR_CB4_MASK 0x00000010
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/* <3>, w/o - check bit 2 (data D<67>) */
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#define DR_CB2_MASK 0x00000008
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/* <2>, w/o - check bit 1 (data D<66>) */
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#define DR_CB1_MASK 0x00000004
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/* <1>, w/o - check bit 1 (data D<65>) */
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#define DR_CB0_MASK 0x00000002
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/* <0>, w/o - check bit X (data D<64>) */
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#define DR_CBX_MASK 0x00000001
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/*
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* To compute the U number of the bad chip on 8meg memory boards we use
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* bits A3 and A22 of the physical address and the bit number calculated
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* from the syndrome. The bit number forms the last two digits of the
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* U number and the address bits are decoded as follows to get the first
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* two digits
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* Physical address lines Data bit U number
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* A3 A22 number prefix
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*
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* 0 0 =<35 U15xx
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* 1 0 =<35 U17xx
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* 0 1 =<35 U19xx
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* 1 1 =<35 U21xx
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*
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* 0 0 =>36 U14xx
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* 1 0 =>36 U16xx
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* 0 1 =>36 U18xx
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* 1 1 =>36 U20xx
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*/
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#define MEG8 0x7fffff /* mask for physical address bits on board */
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#define MEG16 0xffffff /* mask for physical address bits */
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#define MEG32 0x1ffffff /* mask for physical address bits */
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#define LOWER 36 /* divider between upper and lower memory */
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#define ECC_BITS 0x400008 /* mask for physical address bits */
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#define U14XX 0x0
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#define U15XX 0x0
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#define U16XX 0x8
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#define U17XX 0x8
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#define U18XX 0x400000
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#define U19XX 0x400000
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#define U20XX 0x400008
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#define U21XX 0x400008
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/*
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* To compute the U number of the bad chip on 32/16meg memory boards we use
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* bits A3 and A24 of the physical address and the bit number calculated
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* from the syndrome. The bit number forms the last two digits of the
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* U number and the address bits are decoded as follows to get the first
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* two digits
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* Physical address lines Data bit U number
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* A3 A24 number prefix
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*
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* 0 0 0-35 U15xx
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* 1 0 0-35 U17xx
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* 0 1 0-35 U19xx
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* 1 1 0-35 U21xx
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*
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* 0 0 36-72 U14xx
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* 1 0 36-72 U16xx
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* 0 1 36-72 U18xx
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* 1 1 36-72 U20xx
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*/
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#define PEG_ECC_BITS 0x1000008 /* mask for physical address bits */
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#define PEG_U18XX 0x1000000
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#define PEG_U19XX 0x1000000
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#define PEG_U20XX 0x1000008
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#define PEG_U21XX 0x1000008
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#define SYNDERR_BITS "\20\10S32\7S16\6S8\5S4\4S2\3S1\2S0\1SX"
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/*
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* Moonshine memory boards have a "similar but not quite the same"
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* set of bits and registers for control and error handling
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*/
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/* moonshine ecc memory enable register */
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#define MMB_BASE_ADDR 0x0000003f /* base address */
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#define MMB_ENA_BOARD 0x00000040 /* enable memory board */
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#define MMB_ENA_ECC 0x00000080 /* enable ecc */
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#define MMB_ENA_SCRUB 0x00000100 /* enable scrub */
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#define MMB_BDSIZ 0x00000600 /* board size (read only) */
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/* 0 - 32M */
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/* 1 - 128M */
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/* 2,3 - reserved */
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#define MMB_BDSIZ_SHIFT 9 /* shift to right justify board size */
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#define MMB_ENS0 0x00000800 /* ecc chip mode pin 0 */
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#define MMB_ENS1 0x00001000 /* ecc chip mode pin 1 */
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#define MMB_BOARDID 0x0000e000 /* board id (read only) */
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/* moonshine ecc error register (read only) */
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#define MMB_CE_ERROR 0x0000000f /* a correctable error has occured */
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#define MMB_BANK 0x0000000f /* bank number which had error */
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#define MMB_PA_32 0x0fffff00 /* phys address bits for first ce */
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#define MMB_PA_128 0x3fffff00 /* phys address bits for first ce */
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/* really pa bits <26:5> */
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#define MMB_PA_SHIFT 3 /* shift to make pa bits into pa */
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/* moonshine syndrone/check bit register (read only) */
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#define MMB_SC0 0x000000ff /* s/c bits for bank 0 */
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#define MMB_SC1 0x0000ff00 /* s/c bits for bank 1 */
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#define MMB_SC2 0x00ff0000 /* s/c bits for bank 2 */
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#define MMB_SC3 0xff000000 /* s/c bits for bank 3 */
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#endif /*!_sun4_eccreg_h*/
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