129 lines
5.0 KiB
C
129 lines
5.0 KiB
C
/* @(#)buserr.h 1.1 92/07/30 SMI */
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#ifndef _sun4c_buserr_h
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#define _sun4c_buserr_h
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/*
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* Copyright 1987-1989 Sun Microsystems, Inc.
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*/
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/*
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* Definitions related to exception handling on the Sun4c.
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*/
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/*
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* The Synchronous Error register captures the cause(s) of synchronous
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* exceptions given to the CPU. The CPU is notified by assertion
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* of the MEX signal, causing a memory exception trap. Because of
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* prefetch the SE register accumulates errors. The software must verify
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* the type of error manually if multiple bits are set in this register.
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* The SE register is technically read/write for diagnostic purposes, but
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* is treated as read-only by the kernel. It is cleared automatically
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* each time it is read. The SE_RW bit is synchronized with the SVA reg,
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* so it always reflects data pertaining to the cycle latched in the SVA reg.
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* NOTE: for early hardware, certain errors reported in the SE reg will
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* also cause a level 15 interrupt to be generated. The kernel must
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* know to ignore these interrupts.
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*
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* The Synchronous Virtual Address register captures the address of
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* synchronous data faults. It is used in conjunction with the SE reg.
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* It is guaranteed to hold the address of the last data fault to have
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* occurred since the SE reg was read. This is necessary because an
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* instruction pre-fetch to an invalid address can occur before the
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* memory cycle of a load/store instruction to an invalid address, and we
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* need to capture the data associated with the load/store instruction
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* (which is faulting), and not the pre-fetched instruction (whose
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* execution hasn't been attempted yet).
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*
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* The Asynchronous Error register caputures the cause(s) of asynchronous
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* exceptions given to the CPU. The CPU is notified with a level 15 interrupt.
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* Because of the possibility of multiple errors, the ASE register
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* accumulates errors until it is read. It is cleared automatically when
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* it is read. The ASE register is technically read/write for diagnostic
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* purposes, but is treated as read-only by the kernel.
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*
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* The Asynchronous Virtual Address register captures the address of
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* asynchronous data faults. It is used in conjunction with the ASE reg.
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* It is guaranteed to latch the address of the first data fault since
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* it was last cleared. It is cleared automatically each time it is
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* read.
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*
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* [ the following registers are not implemented on all Sun-4Cs ]
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*
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* The Asynchronous Data #1 Register captures the first (or only) data
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* word associated with the first asynchronous write buffer error to
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* have occurred since it was last cleared. It is cleared
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* automatically each time it is read.
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*
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* The Asynchronous Data #2 Register captures the second data word
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* associated with the first asynchronous write buffer error to have
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* occurred since it was last cleared. It is cleared automatically
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* each time it is read. It is only valid when ASE_DBLE is set in the
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* ASE register.
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*/
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#ifndef LOCORE
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struct error_regs {
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u_int sync_error_reg; /* synchronous error reg */
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u_int sync_va_reg; /* synchronous address reg */
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u_int async_error_reg; /* asynchronous error reg */
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u_int async_va_reg; /* asynchronous address reg */
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u_int async_data1_reg; /* asynchronous data 1 reg */
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u_int async_data2_reg; /* asynchronous data 2 reg */
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};
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#endif !LOCORE
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/*
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* Synchronous Error bits.
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*/
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#define SE_RW 0x8000 /* direction of bad cycle (0=read) */
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#define SE_INVALID 0x0080 /* page map was invalid */
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#define SE_PROTERR 0x0040 /* protection error */
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#define SE_TIMEOUT 0x0020 /* bus access timed out */
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#define SE_SBBERR 0x0010 /* Sbus bus error */
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#define SE_MEMERR 0x0008 /* Synchronous memory error */
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#define SE_SIZERR 0x0002 /* size error */
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#define SE_WATCHDOG 0x0001 /* Watchdog reset */
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#define SYNCERR_BITS \
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"\20\20WRITE\10INVALID\7PROTERR\6TIMEOUT\5SBBERR\4MEMERR\2SIZERR\1WATCHDOG"
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/*
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* Asynchronous Error bits.
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*/
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#define ASE_SIZ 0x0300 /* IU transaction size */
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#define ASE_SIZ_SHIFT 8 /* amount to shift by */
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#define ASE_WBACKERR 0x0080 /* buffered write invalid error */
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#define ASE_INVALID 0x0080 /* page map was invalid */
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#define ASE_PROTERR 0x0040 /* protection error */
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#define ASE_TIMEOUT 0x0020 /* buffered write timeout */
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#define ASE_DVMAERR 0x0010 /* dvma cycle error */
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#define ASE_MEMERR 0x0008 /* Asynchronous memory error */
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#define ASE_SBERR 0x0002 /* Sbus bus error */
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#define ASE_MULTIPLE 0x0001 /* Multiple SBus errors detected */
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#define ASE_ERRMASK 0x00b0 /* valid error mask */
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#define ASYNCERR_BITS "\20\10WBACKERR\6TIMEOUT\5DVMAERR"
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/*
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* XXX Due to a bug in the 4/60 cache chip, the ASEVAR isn't properly
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* XXX sign-extended on DVMA asynchronous errors. It is properly
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* XXX extended on asynchronous IU errors.
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*/
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#define ASEVAR_SIGNBIT 0x20000000
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#define ASEVAR_SIGNEXTEND(x) (((x) ^ ASEVAR_SIGNBIT) - ASEVAR_SIGNBIT)
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#define ASE_ERRMASK_70 0x00fb /* valid error mask */
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#define ASYNCERR_BITS_70 \
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"\20\10INVALID\7PROTERR\6TIMEOUT\5DVMAERR\4MEMERR\2SBERR\1MULTIPLE"
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/*
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* Flags to define type of memory error.
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*/
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#define MERR_SYNC 0x0
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#define MERR_ASYNC 0x1
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#endif _sun4c_buserr_h
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