34 lines
1.0 KiB
C
34 lines
1.0 KiB
C
/* @(#)intreg.h 1.1 92/07/30 SMI */
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#ifndef _sun4c_intreg_h
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#define _sun4c_intreg_h
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/*
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* Copyright (c) 1988 by Sun Microsystems, Inc.
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*/
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/*
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* The interrupt register provides for the generation of software
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* interrupts and controls the video and clock hardware interrupts.
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*/
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#define OBIO_INTREG_ADDR 0xF5000000 /* address in obio space */
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#define INTREG_ADDR 0xFFFFA000 /* virtual address we map it to */
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#ifndef LOCORE
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#define INTREG ((u_char *)(INTREG_ADDR))
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#endif !LOCORE
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/*
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* Bits of the interrupt register.
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*/
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#define IR_ENA_CLK14 0x80 /* r/w - enable clock level 14 interrupt */
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#define IR_ENA_CLK10 0x20 /* r/w - enable clock level 10 interrupt */
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#define IR_ENA_LVL8 0x10 /* r/w - enable IPL 8 (SBus IRQ 6) interrupt */
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#define IR_SOFT_INT6 0x08 /* r/w - cause software level 6 interrupt */
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#define IR_SOFT_INT4 0x04 /* r/w - cause software level 4 interrupt */
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#define IR_SOFT_INT1 0x02 /* r/w - cause software level 1 interrupt */
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#define IR_ENA_INT 0x01 /* r/w - enable (all) interrupts */
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#endif /* !_sun4c_intreg_h */
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