71 lines
1.7 KiB
ArmAsm
71 lines
1.7 KiB
ArmAsm
/* @(#)subr.s 1.1 92/07/30 SMI */
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/*
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* Copyright (c) 1988 by Sun Microsystems, Inc.
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*/
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/*
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* General assembly language routines.
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*/
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#include <machine/asm_linkage.h>
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#include <machine/mmu.h>
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#include <machine/enable.h>
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#include <machine/eeprom.h>
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#include "assym.s"
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.seg "text"
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.align 4
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/*
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* Read the ID prom.
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* This is mapped from IDPROM_ADDR for IDPROMSIZE bytes in the
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* kernel virtual address space.
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* XXX - my first sparc assembly code -- may be messed up!!!!
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*/
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ENTRY(getidprom)
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set IDPROM_ADDR, %o1
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clr %o2
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1:
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ldub [%o1 + %o2], %o3 ! get id prom byte
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add %o2, 1, %o2 ! interlock
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stb %o3, [%o0] ! put it out
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cmp %o2, IDPROMSIZE ! done yet?
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bne,a 1b
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add %o0, 1, %o0 ! delay slot
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retl ! leaf routine return
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nop ! delay slot
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/*
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* Flush any write buffers between the CPU and the device at address v.
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* This will force any pending stores to complete, and any exceptions
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* they cause to occur before this routine returns.
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*
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* void
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* flush_writebuffers_to(v)
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* addr_t v;
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*
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*
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* Flush all write buffers in the system.
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*
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* void
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* flush_all_writebuffers();
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*
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* void
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* flush_poke_writebuffers(); /* sun4m compatibility * /
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*
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* We implement this by reading the context register; this will stall
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* until the store buffer(s) are empty, on both 4/60's and 4/70's (and
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* clones). Note that we ignore v on Sun4c.
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*/
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ALTENTRY(flush_all_writebuffers)
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ALTENTRY(flush_poke_writebuffers)
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ENTRY(flush_writebuffers_to)
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set CONTEXT_REG, %o1
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lduba [%o1]ASI_CTL, %g0 ! read the context register
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nop; nop ! two delays for synchronization
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nop; nop ! two more to strobe the trap address
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nop ! and three to empty the pipleine
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retl ! so that any generated interrupt
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nop ! will occur before we return
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