140 lines
3.3 KiB
ArmAsm
140 lines
3.3 KiB
ArmAsm
.ident "@(#)map.s 1.1 92/07/30 SMI"
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!
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! Copyright (c) 1986 by Sun Microsystems, Inc.
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!
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/*
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* Additional memory mapping routines for use by standalone debugger,
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* setpgmap(), getpgmap() are taken from the boot code.
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*/
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#include "assym.s"
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#include <sys/param.h>
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#include <machine/mmu.h>
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#include <machine/pte.h>
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#include <machine/enable.h>
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#include <machine/cpu.h>
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#include <machine/psl.h>
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#include <machine/eeprom.h>
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#include <machine/asm_linkage.h>
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#include <machine/reg.h>
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#include <debug/debug.h>
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.seg "text"
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.align 4
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#define CACHE_LINESHFT 5
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#define CACHE_LINESZ (1<<CACHE_LINESHFT)
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/*
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* Flush a page from the cache.
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*
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* vac_pageflush(vaddr)
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* caddr_t vaddr;
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*/
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ENTRY(vac_pageflush)
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set PAGESIZE/8, %g1
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add %o0, %g1, %o1
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add %o1, %g1, %o2
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add %o2, %g1, %o3
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add %o3, %g1, %o4
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add %o4, %g1, %o5
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add %o5, %g1, %g2
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add %g2, %g1, %g3
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1: deccc CACHE_LINESZ, %g1
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sta %g0, [%o0 + %g1]ASI_FCP
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sta %g0, [%o1 + %g1]ASI_FCP
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sta %g0, [%o2 + %g1]ASI_FCP
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sta %g0, [%o3 + %g1]ASI_FCP
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sta %g0, [%o4 + %g1]ASI_FCP
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sta %g0, [%o5 + %g1]ASI_FCP
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sta %g0, [%g2 + %g1]ASI_FCP
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bne 1b
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sta %g0, [%g3 + %g1]ASI_FCP
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retl
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nop
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/*
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* int ldphys(int paddr)
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* read word of memory at physical address
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* also called "ldphys" by some codes
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*/
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ENTRY(ldphys)
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sethi %hi(_cache), %o1
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ld [%o1 + %lo(_cache)], %o1
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cmp %o1, CACHE_PAC_E ! Viking/E$
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bnz,a 0f ! No,
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lda [%o0]ASI_MEM, %o0 ! dont need AC bit set
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mov %psr, %o1 ! Save %psr in %o1
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andn %o1, PSR_ET, %g1 ! disable traps
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mov %g1, %psr
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nop; nop; nop ! PSR delay
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lda [%g0]ASI_MOD, %o2 ! get MMU CSR, %o2 keeps the saved CSR
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set CPU_VIK_AC, %o3 ! AC bit
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or %o2, %o3, %o3 ! or in AC bit
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sta %o3, [%g0]ASI_MOD ! store new CSR
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lda [%o0]ASI_MEM, %o0
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sta %o2, [%g0]ASI_MOD ! restore CSR;
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mov %o1, %psr ! restore psr; enable traps again
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nop ! PSR delay
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0:
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retl
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nop
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/*
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* void stphys(int paddr, int data)
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* write word of memory at physical address
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*/
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ENTRY(stphys)
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sethi %hi(_cache), %o4
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ld [%o4 + %lo(_cache)], %o4
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cmp %o4, CACHE_PAC_E ! Viking/E$?
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bnz,a 0f ! No, dont need AC bit set
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sta %o1, [%o0]ASI_MEM
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mov %psr, %o4 ! Save %psr in %o4
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andn %o4, PSR_ET, %g1 ! disable traps
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mov %g1, %psr
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nop; nop; nop ! PSR delay
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lda [%g0]ASI_MOD, %o2 ! get MMU CSR, %o2 keeps the saved CSR
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set CPU_VIK_AC, %o3 ! AC bit
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or %o2, %o3, %o3 ! or in AC bit
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sta %o3, [%g0]ASI_MOD ! store new CSR
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sta %o1, [%o0]ASI_MEM
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sta %o2, [%g0]ASI_MOD ! restore CSR;
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mov %o4, %psr ! restore psr; enable traps again
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nop ! PSR delay
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0:
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retl
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nop
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/*
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* void mmu_flushall()
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* flush all entries from TLB
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* XXX - for the moment this will only work with GENERIC SRMMU
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* modules, also MP is not supported.
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*/
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ENTRY(mmu_flushall)
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or %g0, FT_ALL << 8, %o0
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sta %g0, [%o0]ASI_FLPR
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retl
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nop ! let mmu settle ??
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/*
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* int mmu_getctp(void)
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* return current context table pointer
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*/
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ENTRY(mmu_getctp) ! int mmu_getctp(void);
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set RMMU_CTP_REG, %o1 ! get srmmu context table ptr
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retl
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lda [%o1]ASI_MOD, %o0
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