271 lines
7.4 KiB
C
271 lines
7.4 KiB
C
/* @(#)pte.h 1.1 92/07/30 SMI */
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/*
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* Copyright (c) 1989 by Sun Microsystems, Inc.
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*/
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/* Copyright (c) 1988, Sun Microsystems, Inc. All Rights Reserved.
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* Sun considers its source code as an unpublished, proprietary
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* trade secret, and it is available only under strict license
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* provisions. This copyright notice is placed here only to protect
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* Sun in the event the source is deemed a published work. Disassembly,
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* decompilation, or other means of reducing the object code to human
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* readable form is prohibited by the license agreement under which
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* this code is provided to the user or company in possession of this
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* copy
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*
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* RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the
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* Government is subject to restrictions as set forth in subparagraph
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* (c) (1) (ii) of the Rights in Technical Data and Computeer Software
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* clause at DFARS 52.227-7013 and in similar clauses in the FAR and
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* NASA FAR Supplement
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*/
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/* This file (translation_intern.h) contains all the structure
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* and macro definitions for the Sparc Reference MMU as of 17 May, 1988
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*/
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#ifndef _sun4m_pte_h
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#define _sun4m_pte_h
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#ifndef LOCORE
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#include <sys/types.h>
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/*
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* generate a pte in the specified space, for the specified page
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* frame, with the specified permissions, possibly cacheable.
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* note: upper bits of page frame may modify the space value,
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* this is a feature not a bug.
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*/
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extern int vac;
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#define MRPTEOF(s,p,a,c,m,r) (((s)<<28)|((p)<<8)|((c)<<7)|((m)<<6)|((r)<<5)|((a)<<2)|MMU_ET_PTE)
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#define PTEOF(s,p,a,c) MRPTEOF(s,p,a,c,0,0)
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struct pte {
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u_int PhysicalPageNumber:24;
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u_char Cacheable:1;
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u_char Modified:1;
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u_char Referenced:1;
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u_char AccessPermissions:3;
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u_char EntryType:2;
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};
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struct proot {
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u_int rootMap:4;
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u_int rootBoundary:20;
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u_char Cacheable:1;
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u_char Modified:1;
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u_char Referenced:1;
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u_char AccessPermissions:3;
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u_char EntryType:2;
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};
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struct pfirst {
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u_int firstTopMap:4;
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u_int firstMap:8;
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u_int firstBoundary:12;
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u_char Cacheable:1;
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u_char Modified:1;
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u_char Referenced:1;
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u_char AccessPermissions:3;
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u_char EntryType:2;
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};
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struct psecond {
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u_int secondTopMap:12;
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u_int secondMap:6;
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u_int secondBoundary:6;
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u_char Cacheable:1;
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u_char Modified:1;
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u_char Referenced:1;
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u_char AccessPermissions:3;
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u_char EntryType:2;
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};
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union ptes {
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struct pte pte;
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u_int pte_int;
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};
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#endif !(LOCORE)
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#define PTE_ETYPE(a) ((a) & 0x3)
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#define PTE_ETYPEMASK (0x3)
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#define PTE_PERMS(b) (((b) & 0x7) << 2)
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#define PTE_PERMMASK ((0x7 << 2))
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#define PTE_PERMSHIFT (2)
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#define PTE_REF(c) (((c) & 0x1) << 5)
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#define PTE_REF_MASK (0x20)
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#define PTE_MOD(c) (((c) & 0x1) << 6)
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#define PTE_MOD_MASK (0x40)
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#define PTE_RM_MASK (PTE_REF_MASK|PTE_MOD_MASK)
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#define PTE_CACHEABLE(d) (((d) & 0x1) << 7)
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#define PTE_CE_MASK (0x80)
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#define PTE_PFN(p) (((p) & 0xFFFFFF) << 8)
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#define PTE_PFN_MASK (0xFFFFFF00)
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#define PTE_DSI_PPN(d,p) ((((d) & 0x3) << 22) | (p) & 0x3FFFFF)
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#define PTE_DSI_MASK (0xC0000000)
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#define PTE_DSI_MAINMEM 0
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#define PTE_DSI_REGS 1
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#define PTE_DSI_VME16 2
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#define PTE_DSI_VME32 3
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#define pte_valid(pte) (((pte)->EntryType) == MMU_ET_PTE)
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#define pte_konly(pte) (((pte)->AccessPermissions == MMU_STD_SRWX) || \
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((pte)->AccessPermissions == MMU_STD_SRWX))
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#define pte_ronly(pte) (((pte)->AccessPermissions == MMU_STD_SRUR) || \
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((pte)->AccessPermissions == MMU_STD_SXUX) || \
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((pte)->AccessPermissions == MMU_STD_SRXURX) || \
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((pte)->AccessPermissions == MMU_STD_SRX))
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#define MAKE_PFNUM(a) \
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(((struct pte *)(a))->PhysicalPageNumber)
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/* Definitions for EntryType */
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#define MMU_ET_INVALID 0
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#define MMU_ET_PTP 1
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#define MMU_ET_PTE 2
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#define PG_V MMU_ET_PTE
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/* Definitions for AccessPermissions */
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#define MMU_STD_SRUR 0
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#define MMU_STD_SRWURW 1
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#define MMU_STD_SRXURX 2
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#define MMU_STD_SRWXURWX 3
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#define MMU_STD_SXUX 4
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#define MMU_STD_SRWUR 5
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#define MMU_STD_SRX 6
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#define MMU_STD_SRWX 7
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#define MAKE_PROT(v) PTE_PERMS(v)
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#define PG_PROT MAKE_PROT(0x7)
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#define PG_KW MAKE_PROT(MMU_STD_SRWX)
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#define PG_KR MAKE_PROT(MMU_STD_SRX)
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#define PG_UW MAKE_PROT(MMU_STD_SRWXURWX)
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#define PG_URKR MAKE_PROT(MMU_STD_SRUR)
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#define PG_UR MAKE_PROT(MMU_STD_SRUR)
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#define PG_UPAGE MAKE_PROT(MMU_SRWUR)
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#define MMU_STD_PAGEMASK 0xFFFFFF000
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#define MMU_STD_PAGESHIFT 12 /* only maps 35:12 */
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#define MMU_STD_PTPSHIFT 6 /* Pointer is 35:6 */
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#define MMU_STD_PAGESIZE (1 << MMU_STD_PAGESHIFT)
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#define MMU_STD_SEGSHIFT 18
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#define MMU_STD_RGNSHIFT 24
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#define MMU_STD_ROOTMASK 0xFFFFF /* after pageshift */
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#define MMU_STD_ROOTSHIFT 20
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#define MMU_STD_FIRSTMASK 0xFFF
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#define MMU_STD_FIRSTSHIFT 12
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#define MMU_STD_SECONDMASK 0x3F
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#define MMU_STD_SECONDSHIFT 6
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#define MMU_STD_THIRDMASK 0x0
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#define MMU_STD_THIRDSHIFT 0
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#define MMU_STD_THIRDTOP 0xFFF
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#define MMU_STD_SECONDTOP 0x3FFFF
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#define MMU_STD_FIRSTTOP 0xFFFFFF
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#define MMU_ROOT_XTR(a) (((a) & 0xFFFFF000) >> MMU_STD_PAGESHIFT)
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#define MMU_FIRST_XTR(a) (((a)&0x00FFF000) >> MMU_STD_PAGESHIFT)
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#define MMU_SECOND_XTR(a) (((a)&0x0003F000) >> MMU_STD_PAGESHIFT)
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#define MMU_L1_INDEX(a) (((a) & 0xFF000000) >> \
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(MMU_STD_PAGESHIFT + MMU_STD_FIRSTSHIFT))
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#define MMU_L2_INDEX(a) (((a)&0x00FC0000) >> \
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(MMU_STD_PAGESHIFT + MMU_STD_SECONDSHIFT))
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#define MMU_L3_INDEX(a) (((a)&0x0003F000) >> \
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(MMU_STD_PAGESHIFT + MMU_STD_THIRDSHIFT))
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#ifndef LOCORE
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extern struct pte mmu_pteinvalid;
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#endif
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#define MMU_STD_INVALIDPTP (0) /* 0 entry type */
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#define MMU_STD_INVALIDPTE (0) /* 0 entry type */
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/* For vac.s */
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#define SEGMENT_SHIFT (MMU_STD_SECONDSHIFT+MMU_STD_PAGESHIFT)
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#ifndef LOCORE
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/*
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* generate a ptp referencing a table starting at the specified
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* physical address.
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*/
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#define PTPOF(pa) (((((unsigned)(pa))>>MMU_STD_PTPSHIFT)<<2)|MMU_ET_PTP)
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struct ptp {
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u_int PageTablePointer:30;
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u_char EntryType:2; /* Checked for validity */
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};
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union ptpe {
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struct pte pte;
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struct ptp ptp;
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u_int ptpe_int;
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};
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#endif !(LOCORE)
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#define MMU_NPTE_ONE 256 /* 256 PTEs in first level table */
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#define MMU_NPTE_TWO 64
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#define MMU_NPTE_THREE 64
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/* For backwards compatibility */
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#define MAKE_PGT(v) ((v) << 20)
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#define PGT_OBMEM MAKE_PGT(0x0) /* onboard memory */
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#define PGT_OBIO MAKE_PGT(0xF) /* onboard I/O */
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#define PGT_VME_D16 MAKE_PGT(0xC) /* VMEbus 16-bit data */
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#define PGT_VME_D32 MAKE_PGT(0xD) /* VMEbus 32-bit data */
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/*
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* Macros so we can look at page numbers and tell what is on
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* the other end. The function "bustype" is in autoconf.c where
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* it is allowed to know the physical memory layout of the machine,
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* which we SHOULD be getting from the devinfo tree.
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*/
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#define BT_UNKNOWN 1 /* not a defined map area */
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#define BT_OBMEM 2 /* system memory */
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#define BT_OBIO 3 /* on-board devices */
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#define BT_VIDEO 4 /* onboard video */
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#define BT_SBUS 5 /* S-Bus */
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#define BT_VME 6 /* VME Bus */
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#if !defined(LOCORE) && defined(KERNEL)
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/* utilities from autoconf.c */
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extern int bustype();
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/* utilities defined in locore.s */
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extern struct pte Heapptes[];
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extern char Heapbase[];
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extern char Heaplimit[];
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extern struct pte Bufptes[];
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extern char Bufbase[];
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extern char Buflimit[];
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extern struct pte Sysmap[];
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extern char Sysbase[];
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extern struct pte mmap[];
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extern struct pte CMAP1[];
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extern char CADDR1[];
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extern struct pte CMAP2[];
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extern char CADDR2[];
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extern char Syslimit[];
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/*
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* These defines are just here to be an aid
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* for someone that was using these defines.
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*/
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#define Usrptmap Sysmap
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#define usrpt Sysbase
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#endif !defined(LOCORE) && defined(KERNEL)
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#endif /*!_sun4m_pte_h*/
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