424 lines
19 KiB
C
424 lines
19 KiB
C
/* @(#)cg8reg.h 1.1 of 7/30/92, SMI */
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/*
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* cg8reg.h:
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* This file has two incarnations, one for the original P4 TC
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* (IBIS frame) buffer and one for various flavors of the
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* SBus-based TC Card. Which incarnation is presented is
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* dependent upon "sun4c" being defined, or not:
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* if !sun4c use Sun IBIS definitions
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* if sun4c use Sbus TC definitions
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*/
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#ifndef CG8REG_INCLUDED
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#define CG8REG_INCLUDED
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#if !defined(sun4c) && !defined(sun4m)
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/* --------- Board Layout of Ibis 24-bit frame buffer ------------------*/
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#include <machine/param.h>
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#include <sundev/p4reg.h>
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#include <sundev/ramdac.h>
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/*
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* These are the physical offset from the beginning of the P4.
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*/
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#define P4IDREG 0x300000
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/* constants define in p4reg.h */
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#define DACBASE (P4IDREG + P4_COLOR_OFF_LUT)
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#define OVLBASE (P4IDREG + P4_COLOR_OFF_OVERLAY)
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#define ENABASE (P4IDREG + P4_COLOR_OFF_ENABLE)
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#define FBMEMBASE (P4IDREG + P4_COLOR_OFF_COLOR)
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#define PROMBASE (P4IDREG + 0x8000)
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/*
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* The device as presented by the "mmap" system call. It seems to the mmap
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* user that the board begins, at its 0 offset, with the overlay plane,
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* followed by the enable plane and the color framebuffer. At 8MB, there
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* is the ramdac followed by the p4 register and the boot prom.
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*/
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#define CG8_VADDR_FB 0
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#define CG8_VADDR_DAC 0x800000
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#define CG8_VADDR_P4REG (CG8_VADDR_DAC + ctob(1))
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#define CG8_VADDR_PROM (CG8_VADDR_P4REG + ctob(1))
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#define PROMSIZE 0x40000
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/*
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* Some sizes constants for reference only. No one actually use them.
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*/
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#define CG8_WIDTH 1152 /* default width */
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#define CG8_HEIGHT 900 /* default height */
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#define PIXEL_SIZE 4 /* # of bytes per pixel in frame
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* buffer */
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#define BITPERBYTE 8
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#define FBSCAN_SIZE (CG8_WIDTH * PIXEL_SIZE)
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#define OVLSCAN_SIZE (CG8_WIDTH / BITPERBYTE)
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/* screen size in bytes */
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#define FBMEM_SIZE (FBSCAN_SIZE * CG8_HEIGHT)
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#define OVL_SIZE (OVLSCAN_SIZE * CG8_HEIGHT)
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#define CG8_RAMDAC_OMAPSIZE 4
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#define CG8_RAMDAC_CMAPSIZE 256
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/*
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* Constants from <sundev/ramdac.h> which define the structure of 3
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* Brooktree 458 ramdac packed into one 32-bit register.
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*/
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#define CG8_RAMDAC_READMASK RAMDAC_READMASK
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#define CG8_RAMDAC_BLINKMASK RAMDAC_BLINKMASK
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#define CG8_RAMDAC_COMMAND RAMDAC_COMMAND
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#define CG8_RAMDAC_CTRLTEST RAMDAC_CTRLTEST
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/*
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* The following sessions describe the physical device. No software
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* actually uses this model which for initial board bring-up and debugging
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* only. Since the definitions of the structure take no space, we leave
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* them here for future references.
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*/
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union ovlplane {
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u_short pixel[OVLSCAN_SIZE / sizeof (u_short)][CG8_HEIGHT];
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u_short bitplane[OVL_SIZE / sizeof (u_short)];
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};
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struct overlay {
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union ovlplane color;
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u_char pad[ENABASE - OVLBASE - OVL_SIZE];
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union ovlplane enable;
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};
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/* The whole board. We defined fb to be linearly addressable, instead of a
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two dimensional array. Maybe we should use union? */
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struct cg8_board {
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struct ramdac lut; /* start at P4BASE + DACBASE */
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u_char pad1[P4IDREG - DACBASE - sizeof (struct ramdac)];
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u_int p4reg; /* p4 bus register */
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u_char pad2[OVLBASE - P4IDREG - sizeof (u_int)];
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struct overlay ovl; /* overlay planes */
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u_char pad3[FBMEMBASE - OVLBASE - sizeof (struct overlay)];
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union fbunit fb[FBMEM_SIZE / sizeof (union fbunit)];
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};
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#else
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/* ------------------------ SBus TC card --------------------------------*/
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/*
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* Some initial definitions common to all versions of SBus TC Card
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*/
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#ifdef TC1REG_DEBUG
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#include <sys/types.h>
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#include <stdio.h>
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#include <pixrect/pixrect.h>
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#endif TC1REG_DEBUG
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#include <machine/param.h>
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/* Frame Buffer Attributes Description (from SBus TC Card on-board PROMs)
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*/
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typedef struct { /* Fb attributes (from on-board PROM): */
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u_int selection_enable:1; /* 1 if there's a selection enable bit. */
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u_int pip_possible:1; /* 1 if pip option possible. */
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u_int simultaneous_8_24:1; /* 1 if separate luts for 8-bit & 24-bit. */
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u_int monochrome:1; /* 1 if monochrome frame buffer present. */
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u_int selection:1; /* 1 if selection memory present. */
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u_int true_color:1; /* 1 if true color frame buffer present. */
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u_int eight_bit_hardware:1; /* 1 if eight bit frame buffer present. */
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u_int unused:9; /* Unused flag area. */
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u_int model:8; /* Frame buffer model. */
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u_int depth:8; /* Default frame buffer's depth (= 1). */
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} FB_Attribute_Flags;
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#define RASTEROPS_TC 1 /* Value "model": TC 1152x900 card. */
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#define RASTEROPS_TCP 2 /* Value "model": TCP 1152x900 card. */
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#define RASTEROPS_TCS 3 /* Value "model": TCS 640x480 card. */
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#define RASTEROPS_TCL 4 /* Value "model": TCL 1280x1024 card. */
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typedef union { /* Construction for fb attributes: */
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FB_Attribute_Flags flags; /* Representation as flags. */
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int integer; /* Representation as integer. */
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} FB_Attributes;
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/***************************************************************************
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* *********************************************************************** *
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* * * *
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* * Board layout of SBus TCP Card (24-bit frame buffer with * *
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* * Picture in a Picture option. * *
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* * * *
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* *********************************************************************** *
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***************************************************************************/
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#define TC_OMAP_SIZE 4 /* Monochrome lookup table size. */
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#define TC_CMAP_SIZE 256 /* 24-bit lookup table sizes. */
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/*#define TC_RAMDAC_CMAPSIZE TC_CMAP_SIZE /* Alias used by pixrect code. */
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#define TCP_NPLL 16 /* Number of pll registers. */
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typedef union { /* PLL register map: */
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u_char vector[TCP_NPLL]; /* ... registers as a vector. */
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struct { /* ... individual register names. */
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u_char nh_low; /* ... ... low 8 bits of NH register. */
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u_char nh_mid_low; /* ... ... next to low order 8 bits of NH */
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u_char nh_mid_high; /* ... ... next to high order 8 bits of NH */
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u_char nh_high; /* ... ... high order 8 bits of NH. */
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u_char r_low; /* ... ... low 8 bits of R register. */
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u_char r_middle; /* ... ... middle 8 bits of R register. */
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u_char r_high; /* ... ... high order 8 bits of R. */
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u_char s; /* ... ... s register. */
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u_char l; /* ... ... l register. */
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u_char p; /* ... ... p register. */
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u_char ttl_lpf; /* ... ... ttl/lpf register. */
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u_char enable; /* ... ... pll enable register. */
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u_char vco_iring; /* ... ... vco/iring register. */
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u_char rl_clock; /* ... ... rl clock register. */
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u_char s_delay; /* ... ... s delay register. */
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u_char g_delay; /* ... ... g delay register. */
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} registers;
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} PLL_Regs;
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/*
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* Brooktree RAMDAC address layouts:
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*/
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typedef struct { /* Brooktree 457 layout: */
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u_char all_address; /* All 3 RAMDACs' address registers. */
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u_char all_color; /* All 3 RAMDACs' color value registers. */
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u_char all_control; /* All 3 RAMDACs' control registers. */
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u_char all_overlay; /* All 3 RAMDACs' overlay value registers. */
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u_char red_address; /* Red gun RAMDAC's address register. */
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u_char red_color; /* Red gun RAMDAC's color value register. */
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u_char red_control; /* Red gun RAMDAC's control register. */
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u_char red_overlay; /* Red gun RAMDAC's overlay value register. */
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u_char green_address; /* Green gun RAMDAC's address register. */
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u_char green_color; /* Green gun RAMDAC's color value register. */
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u_char green_control; /* Green gun RAMDAC's control register. */
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u_char green_overlay; /* Green gun RAMDAC's overlay value register. */
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u_char blue_address; /* Blue gun RAMDAC's address register. */
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u_char blue_color; /* Blue gun RAMDAC's color value register. */
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u_char blue_control; /* Blue gun RAMDAC's control register. */
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u_char blue_overlay; /* Blue gun RAMDAC's overlay value register. */
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} Bt457_Regs;
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typedef struct { /* Brooktree 463 layout: */
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u_char address_low; /* Address register low order bits. */
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u_char address_high; /* Address register high order bits. */
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u_char control; /* Control/data register. */
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u_char color; /* Color palette register. */
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u_char fill[12]; /* Match up to size of Bt 457 layout. */
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} Bt463_Regs;
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typedef struct { /* Brooktree 473 layout: */
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u_char ram_write_addr; /* Address register: writes to color palette. */
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u_char color; /* Data register for color palette. */
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u_char read_mask; /* Pixel read mask register. */
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u_char ram_read_addr; /* Address register: reads from color palette */
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u_char overlay_write_addr; /* Address register: writes overlay palette. */
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u_char overlay; /* Data register for overlay. */
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u_char control; /* Control register. */
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u_char overlay_read_addr; /* Address register: reads overlay palette. */
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} Bt473_Regs;
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typedef struct { /* Venus frame buffer controller chip layout: */
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u_char control1; /* 00: control register 1. */
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u_char control2; /* 01: control register 2. */
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u_char control3; /* 02: control register 3. */
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u_char control4; /* 03: control register 4. */
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u_char status; /* 04: status register. */
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u_char refresh_interval; /* 05: refresh interval: */
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u_short io_config; /* 06: general i/o config. */
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u_int display_start; /* 08: display start. */
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u_int half_row_incr; /* 0C: half row increment. */
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u_int display_pitch; /* 10: display pitch. */
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u_char cas_mask; /* 14: CAS mask. */
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u_char horiz_latency; /* 15: horizontal latency. */
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u_short horiz_end_sync; /* 16: horizontal end sync. */
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u_short horiz_end_blank; /* 18: horizontal end blank. */
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u_short horiz_start_blank; /* 1A: horizontal start blank. */
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u_short horiz_total; /* 1C: horizontal total. */
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u_short horiz_half_line; /* 1E: horizontal half_line. */
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u_short horiz_count_load; /* 20: horizontal count_load. */
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u_char vert_end_sync; /* 22: vertical end_sync. */
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u_char vert_end_blank; /* 23: vertical end_blank. */
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u_short vert_start_blank; /* 24: vertical start blank. */
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u_short vert_total; /* 26: vertical total. */
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u_short vert_count_load; /* 28: vertical count_load. */
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u_short vert_interrupt; /* 2a: vertical interrupt line. */
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u_short io_general; /* 2c: general i/o. */
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u_char y_zoom; /* 2e: Y Zoom register. */
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u_char soft_register; /* 2f: soft register. */
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} Venus_Regs;
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#define VENUS_TCS_MODEL_A 0x8000 /* io_general: version A of tcs card. */
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#define VENUS_TIMING_MASK 0x6000 /* io_general: timing dip switch values: */
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#define VENUS_TIMING_NATIVE 0x0000 /* ... native (apple) timing. */
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#define VENUS_TIMING_NTSC 0x2000 /* ... ntsc timing. */
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#define VENUS_TIMING_PAL 0x4000 /* ... pal timing. */
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#define VENUS_NO_GENLOCK 0x0020 /* io_general: no genlock source. */
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#define VENUS_SOFT_RESET 0x0010 /* io_general: software reset. */
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#define VENUS_VERT_INT_ENA 1 /* control4: vertical interrupt enabled. */
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#define VENUS_VERT_INT 1 /* status: vertical interrupt pending. */
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/*
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* The device as presented by the "mmap" system call. It seems to the mmap
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* user that the board begins, at its 0 offset, with the overlay plane,
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* followed by the enable plane and the color framebuffer. At 8MB, there
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* is the ramdac followed by the p4 register and the boot prom.
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*/
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#define CG8_VADDR_FB 0
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#define CG8_VADDR_DAC 0x800000
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/*
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* Layout of device registers for controlling the SBus TCS Card:
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*/
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typedef struct {
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Venus_Regs tc_venus; /* Venus chip controlling true color. */
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u_char fill1[0x040-sizeof(Venus_Regs)];
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Venus_Regs mono_venus; /* Venus chip controlling selection/monochrome. */
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u_char fill2[0x040-sizeof(Venus_Regs)];
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Bt473_Regs dac; /* Brootree 473 RAMDAC. */
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} Tcs_Device_Map;
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/*
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*
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* Layout of device registers for controlling the SBus TC, TCP, and
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* TCL Cards
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*
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*/
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typedef struct {
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struct mfb_reg sun_mfb_reg;/* Standard Sun memory frame buffer registers */
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union /* RAMDAC support: */
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{
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Bt457_Regs bt457; /* ... Brooktree 457 (TC, TCP cards.) */
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Bt463_Regs bt463; /* ... Brooktree 463 (TCL cards.) */
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} dacs;
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u_char control_status; /* TC control/status register 0. */
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u_char control_status1; /* TC control/status register 1. */
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u_char fill1[14]; /* Unused. */
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u_short x_source_start; /* X signal start (subset of incoming signal) */
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u_short x_source_end; /* X signal end (subset of incoming signal). */
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u_short x_source_scale; /* X signal scaling:pixel drop rate multiplier*/
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u_short fill2; /* Unused. */
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u_short y_source_start; /* Y signal start (subset of incoming signal) */
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u_short y_source_end; /* Y signal end (subset of incoming signal). */
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u_short y_source_scale; /* Y signal scaling:scan line drop rate mult. */
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u_short fb_pitch; /* # pixels(visible & not) between scan lines */
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u_long pip_start_offset; /* Starting offset in fb to start PIP at. */
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u_char control_status2; /* TC control/status register 2. */
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u_char fill3[11]; /* Unused. */
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PLL_Regs pll; /* PLL registers. */
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} Tc1_Device_Map;
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/* Register "addresses" for Brooktree internal registers. These are written to
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* the address register (xxx_address) to select the internal register to be
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* accessed by reads or writes to the control register (xxx_control).
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*/
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#define BT457_BLINK_MASK 5 /* Blink mask register. */
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#define BT457_COMMAND 6 /* Command register. */
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#define BT457_CONTROL 7 /* Control / test register. */
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#define BT457_READ_MASK 4 /* Read mask register. */
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/* Old style TC card control and status register bit definitions.
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*/
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#define TC1_SELECTION_ENABLE 0x80 /* Turn on selection memory. */
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/* Control Status Register 0 definitions:
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*/
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#define TCP_CSR0_PIP_ONE_SHOT 0x40 /* Set to 1 for one-shot frame capture*/
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#define TCP_CSR0_PIP_IS_ON 0x40 /* 1 on read: pip is turned on. */
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#define TCP_CSR0_PIP_IS_ACTIVE 0x20 /* 1 on read: actively generat. images*/
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#define TCP_CSR0_TURN_PIP_ON 0x20 /* Set to 1 for pip active, 0 to stop */
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#define TCP_CSR0_PIP_INSTALLED 0x10 /* = 1 if pip present in system. */
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#define TCP_CSR0_SOURCE_TYPE_MASK 0x03 /* Mask to get video source value. */
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#define TCP_CSR0_COMPOSITE_SOURCE 0x00 /* ... source is composite (1 wire.) */
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#define TCP_CSR0_S_VIDEO_SOURCE 0x01 /* ... source is s-video (2 wire.) */
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#define TCP_CSR0_RGB_SOURCE 0x02 /* ... source is rgb (3 wire.) */
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/* Control Status Register 1 definitions:
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*/
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#define TCP_CSR1_I2C_DATA 0x80 /* I2C bus interface serial data bit. */
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#define TCP_CSR1_I2C_CLOCK 0x40 /* I2C bus interface clock bit. */
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#define TCP_CSR1_FIELD_ONLY 0x10 /* 1 to make image w/only 1 field. */
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#define TCP_CSR1_NO_PIP 0x02 /* 1 if there is no pip present. */
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#define TCP_CSR1_INPUT_CONNECTED 0x01 /* 1 if pip input connected. */
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/* Control Status Register 2 definitions:
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*/
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#define TCP_CSR2_ALTERNATE_PLL 0x01 /* 1 to use VCR PLL (slow timing.) */
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#define TCP_CSR2_COUNT_DOWN 0x02 /* 1 if addr counts down (hor. flip.) */
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#define TCP_CSR2_FIELD_INVERT 0x04 /* 1 to show odd before even field. */
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/* I-squared C bus device addresses and command definitions:
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*/
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#define I2C_ADDR_EEPROM (u_int)0xa0 /* Device address: eeprom for config. */
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#define I2C_ADDR_DACS (u_int)0x88 /* Device address: d to a converters. */
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#define I2C_DAC0_CMD (u_int)0x00 /* Command: d to a converter 0 control. */
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#define I2C_DAC1_CMD (u_int)0x01 /* Command: d to a converter 1 control. */
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#define I2C_DAC2_CMD (u_int)0x02 /* Command: d to a converter 2 control. */
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#define I2C_DAC3_CMD (u_int)0x03 /* Command: d to a converter 3 control. */
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#define I2C_POD_CMD (u_int)0x08 /* Command: port output data control. */
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#define I2C_POD_NTSC (u_int)0x00 /* Data: ntsc timing - port output data. */
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#define I2C_POD_PAL (u_int)0x14 /* Data: pal timing - port output data. */
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#define I2C_BRIGHTNESS I2C_DAC0_CMD /* Command: access brightness control. */
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#define I2C_CONTRAST I2C_DAC1_CMD /* Command: access contrast control. */
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#define I2C_HUE I2C_DAC3_CMD /* Command: access hue control. */
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#define I2C_SATURATION I2C_DAC2_CMD /* Command: access saturation control. */
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#define I2C_HALF_LEVEL (u_int)0x20 /* Data: half level for d/a converters. */
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/*
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*
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* Layout of EEPROM Storage and Related Structures:
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*
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*/
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typedef struct { /* PIP Initialization record: */
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u_char timing_mode; /* ... timing mode specification. */
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u_char brightness; /* ... d to a converter brightness value. */
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u_char contrast; /* ... d to a converter contrast value. */
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u_char saturation; /* ... d to a converter saturation value. */
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u_char hue; /* ... d to a converter hue value. */
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u_char fill; /* ... *** UNUSED *** */
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u_short x_source_start; /* ... starting pixel of signal in x direction. */
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u_short x_source_end; /* ... ending pixel of signal in x direction. */
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u_short y_source_start; /* ... starting pixel of signal in y direction. */
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u_short y_source_end; /* ... ending pixel of signal in y direction. */
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u_char rgb_brightness; /* ... d to a converter rgb brightness. */
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u_char rgb_contrast; /* ... d to a converter rgb brightness. */
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PLL_Regs pll; /* ... phase lock loop initialization values. */
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} Pip_Init_Record;
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#define EEPROM_FACTORY -1 /* Use factory timing default (loc. 0 in eeprom). */
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#define EEPROM_NTSC 0 /* Default timing mode is NTSC. */
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#define EEPROM_PAL 1 /* Default timing mode is PAL. */
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#define EEPROM_NUM_MODES EEPROM_PAL+1
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typedef struct { /* EEPROM storage layout: */
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u_char default_mode; /* ... Default mode selection. */
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u_char fill[15]; /* ... *** UNUSED *** */
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Pip_Init_Record mode[EEPROM_NUM_MODES]; /* ... NTSC, PAL timing defaults. */
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PLL_Regs d1[EEPROM_NUM_MODES]; /* ... Digital 1 pll timing info. */
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PLL_Regs d2[EEPROM_NUM_MODES]; /* ... Digital 2 pll timing info. */
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} EEPROM_Record;
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#endif /* !sun4c */
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#endif CG8REG_INCLUDED
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