335 lines
14 KiB
C
335 lines
14 KiB
C
/* @(#)zsreg.h 1.1 92/07/30 SMI */
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/*
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* Copyright (c) 1983, 1989 by Sun Microsystems, Inc.
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*/
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/*
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* Zilog 8530 SCC Serial Communications Controller
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*
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* This is a dual uart chip with on-chip baud rate generators.
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* It is about as brain-damaged as the typical modern uart chip,
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* but it does have a lot of features as well as the usual lot of
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* brain damage around addressing, write-onlyness, etc.
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*/
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#ifndef _sundev_zsreg_h
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#define _sundev_zsreg_h
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/*
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* Specify the SPARC interrupt level that will be used by the
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* device driver to do its low level processing.
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* This has a range of 1..15, where 1 is low and 15 is high.
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* Boxes with only eight interrupt levels should divide this
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* by two before establishing the interrupt.
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*/
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#define ZS_SOFT_INT 6
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/*
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* Uart registers:
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*
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* There are 16 write registers and 9 read registers in each channel.
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* As usual, the two channels are ALMOST orthogonal, not exactly. Most regs
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* can only be written to, or read, but not both. To access one, you must
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* first write to register 0 with the number of the register you
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* are interested in, then read/write the actual value, and hope that
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* nobody interrupts you in between.
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*
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* Note that the register&bit assignment is suspiciously like the Intel 8274.
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* Do you think they read each others' data sheets? Can they decode them?
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*/
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/* bits in RR0 */
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#define ZSRR0_RX_READY 0x01 /* received character available */
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#define ZSRR0_TIMER 0x02 /* if R15_TIMER, timer reached 0 */
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#define ZSRR0_TX_READY 0x04 /* transmit buffer empty */
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#define ZSRR0_CD 0x08 /* CD input (latched if R15_CD) */
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#define ZSRR0_SYNC 0x10 /* SYNC input (latched if R15_SYNC) */
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#define ZSRR0_CTS 0x20 /* CTS input (latched if R15_CTS) */
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#define ZSRR0_TXUNDER 0x40 /* (SYNC) Xmitter underran */
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#define ZSRR0_BREAK 0x80 /* received break detected */
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/* bits in RR1 */
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#define ZSRR1_ALL_SENT 0x01 /* all chars fully transmitted */
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#define ZSRR1_PE 0x10 /* parity error (latched, must reset) */
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#define ZSRR1_DO 0x20 /* data overrun (latched, must reset) */
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#define ZSRR1_FE 0x40 /* framing/CRC error (not latched) */
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#define ZSRR1_RXEOF 0x80 /* end of recv sdlc frame */
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/*
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* bits in R/WR2 -- interrupt vector number.
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*
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* NOTE that RR2 in channel A is unmodified, while in channel B it is
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* modified by the current status of the UARTs. (This is independent
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* of the setting of WR9_VIS.) If no interrupts are pending, the modified
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* status is Channel B Special Receive. It can be written from
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* either channel.
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*/
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/*
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* bits in RR3 -- Interrupt Pending flags for both channels (this reg can
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* only be read in Channel A, tho. Thanks guys.)
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*/
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#define ZSRR3_IP_B_STAT 0x01 /* Ext/status int pending, chan B */
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#define ZSRR3_IP_B_TX 0x02 /* Transmit int pending, chan B */
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#define ZSRR3_IP_B_RX 0x04 /* Receive int pending, chan B */
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#define ZSRR3_IP_A_STAT 0x08 /* Ditto for channel A */
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#define ZSRR3_IP_A_TX 0x10
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#define ZSRR3_IP_A_RX 0x20
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/* bits in RR8 -- this is the same as reading the Data port */
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/* bits in RR10 -- DPLL and SDLC Loop Mode status -- not entered */
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/* bits in R/WR12 -- lower byte of time constant for baud rate generator */
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/*
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* The following macro can be used to generate the baud rate generator's
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* time constants. The parameters are the input clock to the BRG (eg,
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* 5000000 for 5MHz) and the desired baud rate. This macro assumes that
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* the clock needed is 16x the desired baud rate.
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*/
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#define ZSTimeConst(InputClock, BaudRate) \
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(short)((((long)InputClock+BaudRate*16) / (2*(long)BaudRate*16)) - 2)
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/* bits in R/WR13 -- upper byte of time constant for baud rate generator */
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/* bits in R/WR15 -- interrupt enables for status conditions */
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#define ZSR15_TIMER 0x02 /* ie if baud rate generator = 0 */
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#define ZSR15_CD 0x08 /* ie transition on CD (car. det.) */
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#define ZSR15_SYNC 0x10 /* ie transition on SYNC (gen purp) */
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#define ZSR15_CTS 0x20 /* ie transition on CTS (clr to send) */
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#define ZSR15_TX_UNDER 0x40 /* (SYNC) ie transmit underrun */
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#define ZSR15_BREAK 0x80 /* ie on start, and end, of break */
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/* Write register 0 -- common commands and Register Pointers */
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#define ZSWR0_REG 0x0F /* mask: next reg to read/write */
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#define ZSWR0_RESET_STATUS 0x10 /* reset status bit latches */
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#define ZSWR0_SEND_ABORT 0x18 /* SDLC: send abort */
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#define ZSWR0_FIRST_RX 0x20 /* in WR1_RX_FIRST_IE, enab next int */
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#define ZSWR0_RESET_TXINT 0x28 /* reset transmitter interrupt */
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#define ZSWR0_RESET_ERRORS 0x30 /* reset read character errors */
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#define ZSWR0_CLR_INTR 0x38 /* Reset Interrupt In Service */
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#define ZSWR0_RESET_RXCRC 0x40 /* Reset Rx CRC generator */
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#define ZSWR0_RESET_TXCRC 0x80 /* Reset Tx CRC generator */
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#define ZSWR0_RESET_EOM 0xC0 /* Reset Tx underrun / EOM */
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/* bits in WR1 */
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#define ZSWR1_SIE 0x01 /* status change master int enable */
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/* Also see R15 for individual enabs */
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#define ZSWR1_TIE 0x02 /* transmitter interrupt enable */
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#define ZSWR1_PARITY_SPECIAL 0x04 /* parity err causes special rx int */
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#define ZSWR1_RIE_FIRST_SPECIAL 0x08 /* r.i.e. on 1st char of msg */
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#define ZSWR1_RIE 0x10 /* receiver interrupt enable */
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#define ZSWR1_RIE_SPECIAL_ONLY 0x18 /* rie on special only */
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#define ZSWR1_REQ_IS_RX 0x20 /* REQ pin is for receiver */
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#define ZSWR1_REQ_NOT_WAIT 0x40 /* REQ/WAIT pin is REQ */
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#define ZSWR1_REQ_ENABLE 0x80 /* enable REQ/WAIT */
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/* There are other Receive interrupt options defined, see data sheet. */
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/* bits in WR2 are defined above as R/WR2. */
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/* bits in WR3 */
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#define ZSWR3_RX_ENABLE 0x01 /* receiver enable */
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#define ZSWR3_RXCRC_ENABLE 0x08 /* receiver CRC enable */
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#define ZSWR3_HUNT 0x10 /* enter hunt mode */
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#define ZSWR3_AUTO_CD_CTS 0x20 /* auto-enable CD&CTS rcv&xmit ctl */
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#define ZSWR3_RX_5 0x00 /* receive 5-bit characters */
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#define ZSWR3_RX_6 0x80 /* receive 6 bit characters */
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#define ZSWR3_RX_7 0x40 /* receive 7 bit characters */
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#define ZSWR3_RX_8 0xC0 /* receive 8 bit characters */
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/* bits in WR4 */
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#define ZSWR4_PARITY_ENABLE 0x01 /* Gen/check parity bit */
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#define ZSWR4_PARITY_EVEN 0x02 /* Gen/check even parity */
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#define ZSWR4_1_STOP 0x04 /* 1 stop bit */
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#define ZSWR4_1_5_STOP 0x08 /* 1.5 stop bits */
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#define ZSWR4_2_STOP 0x0C /* 2 stop bits */
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#define ZSWR4_BISYNC 0x10 /* Bisync mode */
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#define ZSWR4_SDLC 0x20 /* SDLC mode */
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#define ZSWR4_X1_CLK 0x00 /* clock is 1x */
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#define ZSWR4_X16_CLK 0x40 /* clock is 16x */
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#define ZSWR4_X32_CLK 0x80 /* clock is 32x */
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#define ZSWR4_X64_CLK 0xC0 /* clock is 64x */
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/* bits in WR5 */
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#define ZSWR5_TXCRC_ENABLE 0x01 /* transmitter CRC enable */
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#define ZSWR5_RTS 0x02 /* RTS output */
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#define ZSWR5_CRC16 0x04 /* Use CRC-16 for checksum */
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#define ZSWR5_TX_ENABLE 0x08 /* transmitter enable */
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#define ZSWR5_BREAK 0x10 /* send break continuously */
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#define ZSWR5_TX_5 0x00 /* transmit 5 bit chars or less */
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#define ZSWR5_TX_6 0x40 /* transmit 6 bit characters */
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#define ZSWR5_TX_7 0x20 /* transmit 7 bit characters */
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#define ZSWR5_TX_8 0x60 /* transmit 8 bit characters */
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#define ZSWR5_DTR 0x80 /* DTR output */
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/* bits in WR6 -- Sync characters or SDLC address field. */
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/* bits in WR7 -- Sync character or SDLC flag */
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/* bits in WR8 -- transmit buffer. Same as writing to data port. */
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/*
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* bits in WR9 -- Master interrupt control and reset. Accessible thru
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* either channel, there's only one of them.
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*/
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#define ZSWR9_VECTOR_INCL_STAT 0x01 /* Include status bits in int vector */
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#define ZSWR9_NO_VECTOR 0x02 /* Do not respond to int ack cycles */
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#define ZSWR9_DIS_LOWER_CHAIN 0x04 /* Disable ints lower in daisy chain */
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#define ZSWR9_MASTER_IE 0x08 /* Master interrupt enable */
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#define ZSWR9_STAT_HIGH 0x10 /* Modify ivec bits 6-4, not 1-3 */
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#define ZSWR9_RESET_CHAN_B 0x40 /* Reset just channel B */
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#define ZSWR9_RESET_CHAN_A 0x80 /* Reset just channel A */
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#define ZSWR9_RESET_WORLD 0xC0 /* Force hardware reset */
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/* bits in WR10 -- SDLC, NRZI, FM control bits */
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#define ZSWR10_UNDERRUN_ABORT 0x04 /* send abort on TX underrun */
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#define ZSWR10_NRZI 0x20 /* NRZI mode (SDLC) */
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#define ZSWR10_PRESET_ONES 0x80 /* preset CRC to ones (SDLC) */
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/* bits in WR11 -- clock mode control */
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#define ZSWR11_TRXC_XTAL 0x00 /* TRxC output = xtal osc */
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#define ZSWR11_TRXC_XMIT 0x01 /* TRxC output = xmitter clk */
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#define ZSWR11_TRXC_BAUD 0x02 /* TRxC output = baud rate gen */
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#define ZSWR11_TRXC_DPLL 0x03 /* TRxC output = Phase Locked Loop */
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#define ZSWR11_TRXC_OUT_ENA 0x04 /* TRxC output enable (unless input) */
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#define ZSWR11_TXCLK_RTXC 0x00 /* Tx clock is RTxC pin */
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#define ZSWR11_TXCLK_TRXC 0x08 /* Tx clock is TRxC pin */
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#define ZSWR11_TXCLK_BAUD 0x10 /* Tx clock is baud rate gen output */
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#define ZSWR11_TXCLK_DPLL 0x18 /* Tx clock is Phase Locked Loop o/p */
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#define ZSWR11_RXCLK_RTXC 0x00 /* Rx clock is RTxC pin */
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#define ZSWR11_RXCLK_TRXC 0x20 /* Rx clock is TRxC pin */
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#define ZSWR11_RXCLK_BAUD 0x40 /* Rx clock is baud rate gen output */
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#define ZSWR11_RXCLK_DPLL 0x60 /* Rx clock is Phase Locked Loop o/p */
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#define ZSWR11_RTXC_XTAL 0x80 /* RTxC uses crystal, not TTL signal */
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/* bits in WR12 -- described above as R/WR12 */
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/* bits in WR13 -- described above as R/WR13 */
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/* bits in WR14 -- misc control bits, and DPLL control */
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#define ZSWR14_BAUD_ENA 0x01 /* enables baud rate counter */
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#define ZSWR14_BAUD_FROM_PCLK 0x02 /* Baud rate gen src = PCLK not RTxC */
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#define ZSWR14_DTR_IS_REQUEST 0x04 /* Changes DTR line to DMA Request */
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#define ZSWR14_AUTO_ECHO 0x08 /* Echoes RXD to TXD */
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#define ZSWR14_LOCAL_LOOPBACK 0x10 /* Echoes TX to RX in chip */
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#define ZSWR14_DPLL_NOP 0x00 /* These 8 commands are mut. exclu. */
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#define ZSWR14_DPLL_SEARCH 0x20 /* Enter search mode in DPLL */
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#define ZSWR14_DPLL_RESET 0x40 /* Reset missing clock in DPLL */
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#define ZSWR14_DPLL_DISABLE 0x60 /* Disable DPLL */
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#define ZSWR14_DPLL_SRC_BAUD 0x80 /* Source for DPLL is baud rate gen */
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#define ZSWR14_DPLL_SRC_RTXC 0xA0 /* Source for DPLL is RTxC pin */
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#define ZSWR14_DPLL_FM 0xC0 /* DPLL should run in FM mode */
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#define ZSWR14_DPLL_NRZI 0xE0 /* DPLL should run in NRZI mode */
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/* bits in WR15 -- described above as R/WR15 */
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/*
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* UART register addressing
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*
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* It would be nice if they used 4 address pins to address 15 registers,
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* but they only used 1. So you have to write to the control port then
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* read or write it; the 2nd cycle is done to whatever register number
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* you wrote in the first cycle.
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*
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* The data register can also be accessed as Read/Write register 8.
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*/
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#ifndef LOCORE
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#ifndef sun386
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struct zscc_device {
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unsigned char zscc_control;
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unsigned char :8; /* Filler */
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unsigned char zscc_data;
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unsigned char :8; /* Filler */
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};
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#else sun386
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#ifdef SUN386
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struct zscc_device {
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unsigned int zscc_control;
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unsigned int zscc_data;
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};
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#endif SUN386
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#ifdef AT386
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struct zscc_device {
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unsigned char zscc_control;
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unsigned char zscc_data;
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unsigned char :8; /* Filler */
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unsigned char :8; /* Filler */
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};
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#endif AT386
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#endif !sun386
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#define ZS_RINGBITS 8 /* # of bits in ring ptrs */
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#define ZS_RINGSIZE (1<<ZS_RINGBITS) /* size of ring */
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#define ZS_RINGMASK (ZS_RINGSIZE-1)
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#define ZS_RINGFRAC 2 /* fraction of ring to force flush */
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#define ZS_RING_INIT(zap) ((zap)->za_rput = (zap)->za_rget = 0)
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#define ZS_RING_CNT(zap) (((zap)->za_rput - (zap)->za_rget) & ZS_RINGMASK)
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#define ZS_RING_FRAC(zap) (ZS_RING_CNT(zap) >= (ZS_RINGSIZE/ZS_RINGFRAC))
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#define ZS_RING_POK(zap, n) (ZS_RING_CNT(zap) < (ZS_RINGSIZE-(n)))
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#define ZS_RING_PUT(zap, c) \
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((zap)->za_ring[(zap)->za_rput++ & ZS_RINGMASK] = (u_char)(c))
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#define ZS_RING_UNPUT(zap) ((zap)->za_rput--)
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#define ZS_RING_GOK(zap, n) (ZS_RING_CNT(zap) >= (n))
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#define ZS_RING_GET(zap) ((zap)->za_ring[(zap)->za_rget++ & ZS_RINGMASK])
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#define ZS_RING_EAT(zap, n) ((zap)->za_rget += (n))
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/*
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* These flags are shared with mcp_async.c and should be kept in sync.
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*/
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#define ZAS_WOPEN 0x00000001 /* waiting for open to complete */
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#define ZAS_ISOPEN 0x00000002 /* open is complete */
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#define ZAS_OUT 0x00000004 /* line being used for dialout */
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#define ZAS_CARR_ON 0x00000008 /* carrier on last time we looked */
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#define ZAS_STOPPED 0x00000010 /* output is stopped */
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#define ZAS_DELAY 0x00000020 /* waiting for delay to finish */
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#define ZAS_BREAK 0x00000040 /* waiting for break to finish */
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#define ZAS_BUSY 0x00000080 /* waiting for transmission to finish */
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#define ZAS_DRAINING 0x00000100 /*
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* waiting for output to drain
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* from chip
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*/
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#define ZAS_SERVICEIMM 0x00000200 /*
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* queue soft interrupt as soon as
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* receiver interrupt occurs
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*/
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#define ZAS_SOFTC_ATTN 0x00000400 /* check soft carrier state in close */
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#define ZAS_PAUSED 0x00000800 /* MCP: dma interrupted and pending */
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#define ZAS_LNEXT 0x00001000 /* MCP: next input char is quoted */
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struct zsaline {
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int za_flags; /* random flags */
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dev_t za_dev; /* major/minor for this device */
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mblk_t *za_xmitblk; /* block being transmitted from */
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struct zscom *za_common; /* address of zs common data struct */
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tty_common_t za_ttycommon; /* data common to all tty drivers */
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int za_wbufcid; /* id of pending write-side bufcall */
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time_t za_dtrlow; /* time dtr went low */
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short za_needsoft; /* need for software interrupt */
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short za_break; /* break occurred */
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union {
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struct {
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u_char _hw; /* overrun (hw) */
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u_char _sw; /* overrun (sw) */
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} _z;
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u_short uover_overrun;
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} za_uover;
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#define za_overrun za_uover.uover_overrun
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#define za_hw_overrun za_uover._z._hw
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#define za_sw_overrun za_uover._z._sw
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short za_ext; /* modem status change */
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short za_work; /* work to do */
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u_char za_rput; /* producing ptr for input */
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u_char za_rget; /* consuming ptr for input */
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u_char *za_optr; /* output ptr */
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short za_ocnt; /* output count */
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u_char za_flowc; /* startc or stopc to transmit */
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u_char za_rr0; /* for break detection */
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u_char za_ring[ZS_RINGSIZE]; /* circular input buffer */
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};
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#endif /* !LOCORE */
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#endif /*!_sundev_zsreg_h*/
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