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seta75D
2021-10-11 18:37:13 -03:00
commit ff309bfe1c
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40
usr.etc/fpa/microcode/Makefile Normal file
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# @(#)Makefile 1.1 94/10/31 SMI
#Warning: The micro-assembler can use the output of cc only if
# cc is called with one argument!
DEFS= const.h
SRCS= sps.u dps.u xtn.u com.u trig.u tran.u ldp.u reg.u mis.u
GET= sccs get
CFLAGS=-O
all: get_all_file tot.bin tot.map fpa_constants
tot.u: $(DEFS) $(SRCS)
cat $(DEFS) $(SRCS) > temp
/lib/cpp -P temp > tot.u
tot.bin: tot.u
../microassembler/fpas -b tot.bin -r tot.map tot.u >tot.out
.SUFFIXES: .u .out
clean:
rm -f tot.* temp const.h fpa_constants compiler_const.h
const.h: constants
sed -f get_all_file constants > const.h
sources: $(DEFS) $(SRCS)
$(SRCS) constants get_all_file get_compiler_file:
$(GET) $@
fpa_constants: constants
grep "^[sdc]" constants >fpa_constants
install: all
install tot.bin ${DESTDIR}/usr/etc/fpa/fpa_micro_bin
install tot.map ${DESTDIR}/usr/etc/fpa/fpa_micro_map
install fpa_constants ${DESTDIR}/usr/etc/fpa/fpa_constants
compiler_const.h: constants
sed -f get_compiler_file constants > compiler_const.h

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usr.etc/fpa/microcode/com.u Normal file
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528
usr.etc/fpa/microcode/constants Normal file
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/* Constants Data Base
* contains constant name, offset, and hex value
* -used by make file to generate table with name and address
* -used by loader(s?) to download values to addresses
*
* the address of a value is the specified offset added to:
* s.p. constants: 0x400 "s...."
* s.p. coeficients: 0x500 "c_s...."
* d.p. constants: 0x600 "d...."
* d.p. coeficients: 0x700 "c_d...."
*/
/* Constants for common user usage */
/* 0 (zero) */
szero 0 00000000
dzero 0 0000000000000000
/* 1.401298464324817071E-45 2**-150 (minimum subnormal) */
sminsub 1 00000001
/* 4.940656458412465442E-324 2**-1075 (minimum subnormal) */
dminsub 1 0000000000000001
/* 1.175494210692441075E-38 2**-127 - 2**-150 (maximum subnormal) */
smaxsub 2 007FFFFF
/* 2.225073858507200889E-308 2**-1023 - 2**-1075 (maximum subnormal) */
dmaxsub 2 000FFFFFFFFFFFFF
/* 1.175494350822287508E-38 2**-127 (minimum normal) */
sminnorm 3 00800000
/* 2.225073858507201383E-308 2**-1023 (minimum normal) */
dminnorm 3 0010000000000000
/* 3.402823466385288598E+38 2**127 - 2**103 (maximum normal) */
smaxnorm 4 7F7FFFFF
/* 1.797693134862315708E+308 2**1023 - 2**970 (maximum normal) */
dmaxnorm 4 7FEFFFFFFFFFFFFF
/* infinity */
sinf 5 7F800000
dinf 5 7FF0000000000000
/* signalling NaN (Not a Number) */
ssnan 6 7FBFFFFF
dsnan 6 7FF7FFFFFFFFFFFF
/* quiet NaN */
sqnan 7 7FFFFFFF
dqnan 7 7FFFFFFFFFFFFFFF
/* 2.718281745910644531 e */
se 8 402DF854
/* 2.718281828459045091 e */
de 8 4005BF0A8B145769
/* 6.283185482025146484 2*pi */
s2pi 9 40C90FDB
/* 6.283185307179586232 2*pi */
d2pi 9 401921FB54442D18
/* 3.141592741012573242 pi */
spi A 40490FDB
/* 3.141592653589793116 pi */
dpi A 400921FB54442D18
/* 1.570796370506286621 pi/2 */
spio2 B 3FC90FDB
/* 1.570796326794896558 pi/2 */
dpio2 B 3FF921FB54442D18
/* 1.414213538169860840 sqrt(2) */
ssqrt2 C 3FB504F3
/* 1.414213562373095145 sqrt(2) */
dsqrt2 C 3FF6A09E667F3BCD
/* 7.071067690849304199E-1 sqrt(1/2) */
ssqrthalf D 3F3504F3
/* 7.071067811865475727E-1 sqrt(1/2) */
dsqrthalf D 3FE6A09E667F3BCD
/* 1 one */
sone E 3F800000
done E 3FF0000000000000
/* .5 one half */
shalf F 3F000000
dhalf F 3FE0000000000000
/* -1 negative one */
smone 10 BF800000
dmone 10 BFF0000000000000
/* 2 two */
stwo 11 40000000
dtwo 11 4000000000000000
/* 3 three */
sthree B1 40400000
dthree B1 4008000000000000
/* 4 four */
sfour 12 40800000
dfour 12 4010000000000000
/* 8 eight */
seight 13 41000000
deight 13 4020000000000000
/* .5 one half */
s1o2 14 3f000000
d1o2 14 3fe0000000000000
/* .25 one quarter */
s1o4 15 3e800000
d1o4 15 3fd0000000000000
/* .125 one eighth */
s1o8 16 3e000000
d1o8 16 3fc0000000000000
/* 10 ten */
s1e1 17 41200000
d1e1 17 4024000000000000
/* 100 one hundred */
s1e2 18 42c80000
d1e2 18 4059000000000000
/* 1000 one thousand */
s1e3 19 447a0000
d1e3 19 408F400000000000
/* 10000 ten thousand */
s1e4 20 461C4000
d1e4 20 40C3880000000000
/* 100000 one hundred thousand */
s1e5 21 47C35000
d1e5 21 40F86A0000000000
/* 1000000 one million */
s1e6 22 49742400
d1e6 22 412E848000000000
/* 10000000 ten million */
s1e7 23 4B189680
d1e7 23 416312D000000000
/* 100000000 one hundred million */
s1e8 24 4CBEBC20
d1e8 24 4197D78400000000
/* 1000000000 one billion */
s1e9 25 4E6E6B28
d1e9 25 41CDCD6500000000
/* 10000000000 ten billion */
s1e10 26 501502F9
d1e10 26 4202A05F20000000
/* -1.570796370506286621 -pi/2 */
smpio2 27 BFC90FDB
/* -1.570796326794896558 -pi/2 */
dmpio2 27 BFF921FB54442D18
/* 1.442695021629333496 log2(e) */
slog2e 28 3FB8AA3B
/* 1.442695040888963387 log2(e) */
dlog2e 28 3FF71547652B82FE
/* 3.321928024291992188 log2(10) */
slog2ten 29 40549A78
/* 3.321928094887362182 log2(10) */
dlog2ten 29 400A934F0979A371
/* 6.931471824645996094E-1 loge(2) */
slogetwo 2A 3F317218
/* 6.931471805599452862E-1 loge(2) */
dlogetwo 2A 3FE62E42FEFA39EF
/* 2.302585124969482422 loge(10) */
slogeten 2B 40135D8E
/* 2.302585092994045901 loge(10) */
dlogeten 2B 40026BB1BBB55516
/* 3.010300099849700928E-1 log10(2) */
slog10two 2C 3E9A209B
/* 3.010299956639811980E-1 log10(2) */
dlog10two 2C 3FD34413509F79FF
/* 4.342944920063018799E-1 log10(e) */
slog10e 2D 3EDE5BD9
/* 4.342944819032518167E-1 log10(e) */
dlog10e 2D 3FDBCB7B1526E50E
/* -.5 -1/2 */
smhalf 2E BF000000
dmhalf 2E BFE0000000000000
/* 1.000000027256422400E+16 10**16 */
s1e16 2F 5A0E1BCA
/* 1.000000000000000000E+16 10**16 */
d1e16 2F 4341C37937E08000
/* 1.000000033181353514E+32 10**32 */
s1e32 30 749DC5AE
/* 1.000000000000000054E+32 10**32 */
d1e32 30 4693B8B5B5056E17
/* infinity 10**64 */
s1e64 31 7f800000
/* 1.000000000000000021E+64 10**64 */
d1e64 31 4D384F03E93FF9F5
/* infinity 10**128 */
s1e128 32 7f800000
/* 1.000000000000000075E+128 10**128 */
d1e128 32 5A827748F9301D32
/* infinity 10**256 */
s1e256 33 7f800000
/* 1.000000000000000030E+256 10**256 */
d1e256 33 75154FDD7F73BF3C
/* 4.375000000000000000E-1 7/16 */
s7o16 34 3ee00000
/* 6.875000000000000000E-1 11/16 */
s11o16 35 3f300000
/* 1.187500000000000000 19/16 */
s19o16 36 3f980000
/* 2.437500000000000000 39/16 */
s39o16 37 401C0000
/* Constants for transcendentals */
/* following location saved for checksum */
c_dchecksum FF 0000000000000000
/* Holds the correct value of the mode register except in FAST mode (used in e**x) */
c_dmode_fast F4 0000000355555555
/* Holds the current value of the mode (bits 0 - 3) register */
c_dmode F3 FFFFFFF055555555
/* Holds the correct value of the mode register (for transcendentals) */
c_dmode_cor F2 0000000255555555
/* Constants revision no. (0000XYVN00mmddyy, release X.Y, Nth cut of V version) */
c_dconst_rev F1 000041A100060988
/* Microcode revision no. */
c_ducode_rev F0 000041A100110889
/* Scratch-Pad Area */
c_dSCRATCH_0 D0 0000000000000000
c_dSCRATCH_1 D1 0000000000000000
c_dSCRATCH_2 D2 0000000000000000
c_dSCRATCH_3 D3 0000000000000000
c_dSCRATCH_4 D4 0000000000000000
c_dSCRATCH_5 D5 0000000000000000
c_dSCRATCH_6 D6 0000000000000000
c_dSCRATCH_7 D7 0000000000000000
c_dSCRATCH_8 D8 0000000000000000
c_dSCRATCH_9 D9 0000000000000000
c_dSCRATCH_10 DA 0000000000000000
c_dSCRATCH_11 DB 0000000000000000
c_dSCRATCH_12 DC 0000000000000000
c_dSCRATCH_13 DD 0000000000000000
c_dSCRATCH_14 DE 0000000000000000
c_dSCRATCH_15 DF 0000000000000000
c_dSCRATCH_31 EF 0000000000000000
/* All values below here do not change after download; they are */
/* checksum'ed */
c_spi3o4 CE 4016CBE4
c_dpi3o4 CE 4002D97C7F3321D2
c_spi5o4 CD 407B53D1
c_dpi5o4 CD 400F6A7A2955385E
c_so2pi CC 3E22F983
c_do2pi CC 3FC45F306DC9C883
c_spi2p21 CB 4AC90FDB
c_dpi2p21 CB 415921FB54442D18
c_spio2b24a C9 3FC90FDB
c_spio2b24b C8 B33BBD2E
c_dpio2b33a C9 3FF921FB54400000
c_dpio2b33b C8 3DD0B4611A600000
c_spib24a C7 40490FDB
c_spib24b C6 B3BBBD2E
c_dpib33a C7 400921FB54400000
c_dpib33b C6 3DE0B4611A600000
c_d2pib33a C5 401921FB54400000
c_d2pib33b C4 3DF0B4611A600000
c_stwop20 BF 49800000
c_stwop23 BE 4B000000
c_stwop26 BD 4D800000
c_stwopm12 BC 39800000
c_stwopm13 BB 39000000
c_stwopm14 BA 38800000
c_stwopm20 B9 35800000
c_stwopm21 B8 35000000
c_stwopm23 B7 34000000
c_stwopm24 B6 33800000
c_stwopm25 B5 33000000
c_stwopm26 B4 32800000
c_dtwop52 BF 4330000000000000
c_dtwop54 BE 4350000000000000
c_dtwopm27 BC 3E40000000000000
c_dtwopm28 BB 3E30000000000000
c_dtwopm54 BA 3C90000000000000
c_dmtwopm54 B9 BC90000000000000
c_s127 AF 42FE0000
c_s87 AE 42AE0000
c_sloge2a AD 3F317200
c_sloge2b AC 35BFBE8E
c_dloge2a AD 3FE62E42FEF00000
c_dloge2b AC 3DD473DE6AF00000
c_ssqrthalfm1 AB BE95F61A
c_ssqrt2m1 AA 3ED413CD
/* Status */
c_sinexact A9 00000300
c_szerostat A8 00000000
c_sexact A7 00000200
c_smaxmode A6 0000000F
c_s63 A5 427C0000
c_s53 A4 42540000
c_d708 A3 4086200000000000
c_s1023 A2 447FC000
c_s3o2 A1 3FC00000
c_d3o2 A1 3FF8000000000000
c_s511 A0 43FF8000
c_sfourth 9F 3E800000
c_dfourth 9F 3FD0000000000000
c_sthreshold 9E 38800000
c_stwo19pi 9D 49C90FDB
c_scosthresh 9C 3E85B863
c_stwoopi 9B 3F22F983
c_dtwopia 9A 401921FB54400000
c_dtwopib 99 3DF0B4611A600000
c_dpia 98 400921FB54400000
c_dpib 97 3DE0B4611A600000
c_dpio2a 96 3FF921FB54400000
c_dpio2b 95 3DD0B4611A600000
c_dmpib 94 BDE0B4611A600000
c_dmpio2b 93 BDD0B4611A600000
c_dtwo19pi 92 413921FB54442D18
c_dcosthresh 91 3FD0B70C6D604DD4
c_dthreshold 90 3E30000000000000
c_dtwoopi 8F 3FE45F306DC9C883
c_smaxln 8E 7EFFFFBF
c_dmaxln 8E 7FDFFFBFFFFFFFFF
c_dsqrt2m1 8D 3FDA827999FCEF32
c_dsqrt8m1 8C 3FFD413CCCFE7799
c_dsqrteighthm1 8B BFE4AFB0CCC0621A
c_dloge2afrom1 8A 3FD3A37A02200000
c_dloge2amhalf 89 3FC8B90BFBC00000
c_dsqrthalfm1 88 BFD2BEC333018867
c_dsqrt2p1 87 4003504F333F9DE6
c_dpio4a 86 3FE921FB54400000
c_dpio4b 85 3DC0B4611A600000
c_dtestsolution1 84 BCB0000000000000
c_dtestsolution2 83 BCC0000000000000
c_spio4 82 3F490FDB
c_dpio4 82 3FE921FB54442D18
c_soberr 81 00000400
/* constants for s.p. atan */
c_satan_small 4F 3089705F
c_satan_big 4E 5368D4A5
c_satan_hhilo 4D 3EED6338
c_satan_hhilob 4C 31AC376A
c_satan_mhhilo 4B BEED6338
c_satan.mhhilob 4A B1AC376A
c_satan_lhilo 49 3F7B985F
c_satan_lhilob 48 B2D7E096
c_satan_mlhilo 47 BF7B985F
c_satan_mlhilob 46 32D7E096
c_satan_00 45 00000000
c_satan_00b 44 00000000
c_satan_40 43 3F490FDB
c_satan_40b 42 B2BBBD2E
c_satan_m40 41 BF490FDB
c_satan_m40b 40 32BBBD2E
c_satan_20 3F 3FC90FDB
c_satan_20b 3E B33BBD2E
c_satan_m20 3D BFC90FDB
c_satan_m20b 3C 333BBD2E
/* constants for d.p. atan */
c_sdatan_small 3B 3089705F
c_sdatan_big 3A 5D5E0B6B
c_datan_hhilo 4D 3FDDAC670561BB4F
c_datan_hhilob 4C 3C55543B8F253271
c_datan_mhhilo 4B BFDDAC670561BB4F
c_datan_mhhilob 4A BC55543B8F253271
c_datan_lhilo 49 3FEF730BD281F69B
c_datan_lhilob 48 BC7C23DFEFEAE6B5
c_datan_mlhilo 47 BFEF730BD281F69B
c_datan_mlhilob 46 3C7C23DFEFEAE6B5
c_datan_00 45 0000000000000000
c_datan_00b 44 0000000000000000
c_datan_40 43 3FE921FB54400000
c_datan_40b 42 3DC0B4611A600000
c_datan_m40 41 BFE921FB54400000
c_datan_m40b 40 BDC0B4611A600000
c_datan_20 3F 3FF921FB54400000
c_datan_20b 3E 3DD0B4611A600000
c_datan_m20 3D BFF921FB54400000
c_datan_m20b 3C BDD0B4611A600000
/* Coeficients */
/* Sine */
c_ssin0 0 BE2AAAA0
c_ssin1 1 3C088302
c_ssin2 2 B94C7DC9
c_dsin0 0 BFC555555555550C
c_dsin1 1 3F8111111110C461
c_dsin2 2 BF2A01A019746345
c_dsin3 3 3EC71DE3209CDCD9
c_dsin4 4 BE5AE5C0E319A4EF
c_dsin5 5 3DE5CF61DF672B13
/* Cosine */
/* for positive calculations */
c_scosz2 6 BF000000
c_scosz1 7 3F800000
c_scos0 8 3D2AAA9C
c_scos1 9 BAB60376
c_scos2 A 37CC73EE
c_dcosz2 6 BFE0000000000000
c_dcosz1 7 3FF0000000000000
c_dcos0 8 3FA555555555553E
c_dcos1 9 BF56C16C16C14199
c_dcos2 A 3EFA01A01971CAEB
c_dcos3 B BE927E4F1314AD1A
c_dcos4 C 3E21EE3B60DDDC8C
c_dcos5 D BDA8BD5986B2A52E
/* for negative calculations */
c_sncosz2 E 3F000000
c_sncosz1 F BF800000
c_sncos0 10 BD2AAA9C
c_sncos1 11 3AB60376
c_sncos2 12 B7CC73EE
c_dncosz2 E 3FE0000000000000
c_dncosz1 F BFF0000000000000
c_dncos0 10 BFA555555555553E
c_dncos1 11 3F56C16C16C14199
c_dncos2 12 BEFA01A01971CAEB
c_dncos3 13 3E927E4F1314AD1A
c_dncos4 14 BE21EE3B60DDDC8C
c_dncos5 15 3DA8BD5986B2A52E
/* Tangent */
/* c_stan0 32 3EAAAAB3 */
/* c_stan1 33 3E088668 */
/* c_stan2 34 3D5D79A0 */
/* c_stan3 35 3CADF9C5 */
/* c_stan4 36 3C331D70 */
/* c_stan5 37 B783FE7C */
/* c_stan6 38 3B90E77B */
/* tan0 through tan 6 are q(0) - q(3) and p(1) - p(3) */
/* c_dtanq1 39 C13EA0D0D16BCB12 */
/* c_dtanq2 3A 412C96E19FD8E8DF */
/* c_dtanq3 3B C0E927364E1119ED */
/* c_dtanq4 3C 40838F20A0402411 */
/* c_dtanp1 3D C1246B35E0F28761 */
/* c_dtanp2 3E 40E5CBE30A30668F */
/* c_dtanp3 3F C082704DE7C2735C */
/* Inverse Tangent */
/* itn0 through itn 7 are q(0) - q(4) and p(1) - p(3) */
/* c_ditn0 49 40EB56360FD50554 */
/* c_ditn1 4A C0D9845DAD0EA7FF */
/* c_ditn2 4B 4096733AB870A316 */
/* c_ditn3 4C C031750AC591202D */
/* c_ditn4 4D 3F9C8FA7E609A1DB */
/* c_ditn5 4E C0EB56360FD50554 */
/* c_ditn6 4F 40BD2B9134AD3C71 */
/* c_ditn7 50 C067F7D4A1BF238C */
/* Arctangent */
/* c_satn1 16 BEAAAA9A */
/* c_satn2 17 3E4CC841 */
/* c_satn3 18 BE120ACD */
/* c_satn4 19 3DE017C1 */
/* c_satn5 1A BDAB9142 */
/* c_satn6 1B 3D6BBBC1 */
/* c_satn7 1C BCFC59EC */
/* c_satn8 1D 3C2FC010 */
/* c_satn9 1E BAE5E421 */
c_satan_c1 16 3EAAAA9A
c_satan_c2 17 BE4CC841
c_satan_c3 18 3E120ACD
c_satan_c4 19 BDE017C1
c_satan_c5 1A 3DAB9142
c_satan_c6 1B BD6BBBC1
c_satan_c7 1C 3CFC59EC
c_satan_c8 1D BC2FC010
c_satan_c9 1E 3AE5E421
/* Arc Tangent */
/* c_datan1 16 BFD5555555555531 */
/* c_datan2 17 3FC99999999948f9 */
/* c_datan3 18 BFC2492492268309 */
/* c_datan4 19 3FBC71C70D0B85EF */
/* c_datan5 1A BFB745CF6DC23936 */
/* c_datan6 1B 3FB3B10FA5A8FD96 */
/* c_datan7 1C BFB10EA8309B0CE9 */
/* c_datan8 1D 3FADEFF7AC18EAD0 */
/* c_datan9 1E BFA9C91CE88DAA9B */
/* c_datan10 1F 3FA373DCC009851B */
/* c_datan11 20 BF92435BE5B3C8B0 */
c_datan_c1 16 3FD55555555555C3
c_datan_c2 17 BFC9999999997CCD
c_datan_c3 18 3FC24924921EC1D7
c_datan_c4 19 BFBC71C7059AF280
c_datan_c5 1A 3FB745CE5AA35DB2
c_datan_c6 1B BFB3B0FA54BEC400
c_datan_c7 1C 3FB10DA924597FFF
c_datan_c8 1D BFADE125FDDBD793
c_datan_c9 1E 3FA9860524BDD807
c_datan_c10 1F BFA2CA6C04C6937A
c_datan_c11 20 3F90D52174A1BB54
/* Exponential */
c_sexps1 21 C2705E31
c_sexps2 22 41203EBB
c_sexpt1 23 C2F05E31
c_sexpt2 24 42705E31
c_sexpt3 25 C1403EBB
/* Exponential */
c_dexps1 21 C0CD8DAA5E475F3C
c_dexps2 22 40A3B3C6E984E9BF
c_dexps3 23 C07A4450E84585FE
c_dexps4 24 403C0373AC7AAEBB
c_dexpt1 25 C0DD8DAA5E475F3C
c_dexpt2 26 40CD8DAA5E475F3C
c_dexpt3 27 C0AA44DB23964B3E
c_dexpt4 28 407A4450E84585FE
c_dexpt5 29 C03E0373AC7AAEBB
/* Logarithm */
c_slogs1 2A 3F2AAADA
c_slogs2 2B 3ECC9FF7
c_slogs3 2C 3E9A1D1A
/* Logarithm */
c_dlogs1 2A 3fe5555555555592
c_dlogs2 2B 3fd999999997ff24
c_dlogs3 2C 3fd24924941e07b4
c_dlogs4 2D 3fcc71c52150bea6
c_dlogs5 2E 3fc74663cc94342f
c_dlogs6 2F 3fc39a1ec014045b
c_dlogs7 30 3fc2f039f0085122
/* Square Root */
/* c_ssqrts1 59 4082CF42 */
/* c_ssqrts4 5A 3F37AAB2 */
/* c_ssqrts2 5B C0CAA824 */
/* c_ssqrts5 5C BFC97191 */
/* c_ssqrts3 5D 4193C0B9 */
/* c_ssqrtr1 5E 3F38FE23 */
/* c_ssqrtr4 5F 4037AAB2 */
/* c_ssqrtr2 60 BF0F4CCD */
/* c_ssqrtr5 61 C0497191 */
/* c_ssqrtr3 62 3F50F43C */
/* Test Data Area */
c_dtest 50 4000000000000000
c_dtest1 51 BFFFFFFFFFFFFFFF
c_dtest2 52 BFFFFFFFFFFFFFFF
c_dtest3 53 4000000000000000
c_dtest4 54 BFFFFFFFFFFFFFFF
c_dtest5 55 4000000000000000
c_dtest6 56 4000000000000000
c_dtest7 57 BFFFFFFFFFFFFFFF
c_dtest8 58 BFFFFFFFFFFFFFFF
c_dtest9 59 4000000000000000
c_dtesta 5A 4000000000000000
c_dtestb 5B BFFFFFFFFFFFFFFF
c_dtestc 5C 4000000000000000
c_dtestd 5D BFFFFFFFFFFFFFFF
c_dteste 5E BFFFFFFFFFFFFFFF
c_dtestf 5F 4000000000000000
c_dtest10 60 BFFFFFFFFFFFFFFF
c_dtest11 61 4000000000000000
c_dtest12 62 4000000000000000
c_dtest13 63 BFFFFFFFFFFFFFFF
c_dtest14 64 4000000000000000
c_dtest15 65 BFFFFFFFFFFFFFFF
c_dtest16 66 BFFFFFFFFFFFFFFF
c_dtest17 67 4000000000000000
c_dtest18 68 4000000000000000
c_dtest19 69 BFFFFFFFFFFFFFFF
c_dtest1a 6A BFFFFFFFFFFFFFFF
c_dtest1b 6B 4000000000000000
c_dtest1c 6C BFFFFFFFFFFFFFFF
c_dtest1d 6D 4000000000000000
c_dtest1e 6E 4000000000000000
c_dtest1f 6F BFFFFFFFFFFFFFFF

193
usr.etc/fpa/microcode/dps.u Normal file
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|*
|* Nop Instruction
|*
routine dp.nop w000000xxxx1 lnop sneg
; ; ; ; ;
jclr clp idl2; ; ; ; ;
call idle1; ; ; ; ;
|*
|* Double Precision Negate Instruction
|* Double Precision Absolut Value Instruction
|*
routine dp.neg w000001xxxx1 lam dneg
routine dp.abs w000010xxxx1 lam dabs
jclr clp1 idl2; lalf fmap csla; opdlsw; ; ;
; ; ; recclk; rcsmsw ptr2;
; ; ; recclk; rcslsw ptr2;
dfin.alu:
; ; ; ; ;
dfin.alu2:
; csuxa umsw; ; ; ;
; csuxa ulsw; ; ; ptr2;
jwerr der2 cstat;woea; dtor; ; ramwe rcsmsw ptr2;
; woea; dtor; ; ramwe rcslsw ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Double Precision Fix Instruction (convert to integer)
|*
routine dp.fix w000100xxxx1 lam dcvtint
jclr clp1 idl2; lalf dcvtint csla; opdlsw; ; ;
; ; ; ; ;
; ; ; ; ;
; ; ; ; ;
; csuxa ulsw; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woea; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Double Precision Float Instruction
|*
routine dp.float w000011xxxx1 lal dfloat
; lalf fmap csla; opdmsw; ; ;
; ; ; recclk; rcsmsw ptr2;
; ; ; recclk; rcslsw ptr2;
; ; ; ; ;
jclr clp idl2; csuxa umsw; ; ; ;
; csuxa ulsw; ; ; ptr2;
jwerr der2 cstat;woea; dtor; ; ramwe rcsmsw ptr2;
; woea; dtor; ; ramwe rcslsw ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Double Precision Convert Instruction
|*
routine dp.conv w000101xxxx1 lam dcvts
jclr clp1 idl2; lalf fmap csla; opdlsw; ; ;
; ; ; ; ;
; ; ; ; ;
; ; ; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woea; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Double Precision Square Instruction
|*
routine dp.sqar w000110xxxx1 lam dmul
; lbm cslm; opdmsw; ; ;
jclr clp3 idl2; lal cslm; opdlsw; ; ;
; lblf fmap cslm; opdlsw; ; ;
; ; ; recclk; rcsmsw ptr2;
; ; ; recclk; rcslsw ptr2;
dfin.mul:
; ; ; ; ;
; ; ; ; ;
; ; ; ; ;
; csuxm umsw; ; ; ;
; csuxm ulsw; ; ; ptr2;
jwerr der2 cstat;woem; dtor; ; ramwe rcsmsw ptr2;
; woem; dtor; ; ramwe rcslsw ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Double Precision Add Instruction
|* Double Precision Subtract Instruction
|*
routine dp.add w000111xxxx1 lbm dadd
routine dp.sub w001000xxxx1 lbm dsub
; lam csla; reg; recclk; rcslsw ptr2;
; lal csla; reg; ; ;
jclr clp1 idl2; lblf fmap csla; opdlsw; ; ;
; ; ; ; ;
call dfin.alu; ; ; ; ;
| ; ; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr2;
| jwerr der2 cstat;woea; dtor; ; ramwe rcsmsw ptr2;
| ; woea; dtor; ; ramwe rcslsw ptr2;
| call idle1; ; dtor; ; ramwe ptr2;
|*
|* Double Precision Multiply Instruction
|*
routine dp.mul w001001xxxx1 lbm dmul
; lam cslm; reg; recclk; rcslsw ptr2;
; lal cslm; reg; ; ;
| Note: the reason we don't do a minimum latency multiply,
| is so we can delay idle2 as long as possible
jclr clp3 idl2; lblf fmap cslm; opdlsw; ; ;
; ; ; ; ;
call dfin.mul; ; ; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxm umsw; ; ; ;
| ; csuxm ulsw; ; ; ptr2;
| jwerr der2 cstat;woem; dtor; ; ramwe rcsmsw ptr2;
| ; woem; dtor; ; ramwe rcslsw ptr2;
| call idle1; ; dtor; ; ramwe ptr2;
|*
|* Double Precision Divide Instruction
|*
routine dp.div w001010xxxx1 lbm ddiv
; lam csla; reg; recclk; rcslsw ptr2;
; lal csla; reg; ; ;
jclr clp56 idl2;lblf fmap csla; opdlsw; ; ;
|# (Note: 26 will cause a delay of 54)
; ; ; ; ; lpreg!26
call wait; ; ; ; ;
call dfin.alu2; ; ; ; ;
| ; ; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr2;
| jwerr der2 cstat;woea; dtor; ; ramwe rcsmsw ptr2;
| ; woea; dtor; ; ramwe rcslsw ptr2;
| call idle1; ; dtor; ; ramwe ptr2;
|*
|* Double Precision Backwards Subtract Instruction
|*
routine dp.b.sub w001011xxxx1 lam dsub
; lbm csla; reg; recclk; rcslsw ptr2;
; lbl csla; reg; ; ;
jclr clp1 idl2; lalf fmap csla; opdlsw; ; ;
; ; ; ; ;
call dfin.alu; ; ; ; ;
| ; ; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr2;
| jwerr der2 cstat;woea; dtor; ; ramwe rcsmsw ptr2;
| ; woea; dtor; ; ramwe rcslsw ptr2;
| call idle1; ; dtor; ; ramwe ptr2;
|*
|* Double Precision Backwards Divide Instruction
|*
routine dp.div w001100xxxx1 lam ddiv
; lbm csla; reg; recclk; rcslsw ptr2;
; lbl csla; reg; ; ;
jclr clp56 idl2;lalf fmap csla; opdlsw; ; ;
|# (Note: 26 will cause a delay of 54)
; ; ; ; ; lpreg!26
call wait; ; ; ; ;
call dfin.alu2; ; ; ; ;
| ; ; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr2;
| jwerr der2 cstat;woea; dtor; ; ramwe rcsmsw ptr2;
| ; woea; dtor; ; ramwe rcslsw ptr2;
| call idle1; ; dtor; ; ramwe ptr2;
|*
|* Double Precision Compare With Zero
|*
routine dp.eqlzero w001101xxxx1 lam dcmp0
jclr clp1 idl2; lalf fmap csla; opdlsw; ; ;
call dfin.cmp; ; ; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa umsw; ; ; ;
| ; ; ; ; ;
| jwerr werr cstat;woea; ; ; ;
| call idle1; ; ; ; ;
|*
|* Double Precision Compare With Reg 1
|* Double Precision Compare Magnitude With Reg 1
|*
routine dp.eqlreg1 w001110xxxx1 lbm dcmp
routine dp.cmpreg1 w001111xxxx1 lbm dcmpm
; lam csla; reg; ; rcslsw ptr2;
; lal csla; reg; ; ;
jclr clp1 idl2; lblf fmap csla; opdlsw; ; ;
; ; ; ; ;
dfin.cmp:
; ; ; ; ;
; ; ; ; ;
; csuxa umsw; ; ; ;
; ; ; ; ;
jwerr werr cstat;woea; ; ; ;
call idle1; ; ; ; ;

224
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/* @(#)fpa.h 1.1 94/10/31 SMI */
/*
* Copyright (c) 1985 by Sun Microsystems, Inc.
*/
#define fpa_debug 1
/*
* This file contains definitions related to the Floating Point
* Accelerator used for the Sun-3 machines.
*/
#ifdef KERNEL
#include "../machine/reg.h"
#else
#include <machine/reg.h>
#endif
/*
* open("/dev/fpa", filemode, createmode) returns ENXIO if there is
* no FPA or 68881 attached. It returns EBUSY if there is no FPA
* context available.
*/
/* ioctl commands */
#define FPA_ACCESS_ON _IO(p, 1)
#define FPA_ACCESS_OFF _IO(p, 2)
#define FPA_LOAD_ON _IO(p, 3)
#define FPA_LOAD_OFF _IO(p, 4)
#define FPA_NSHAD_REGS 8
#define FPA_NDATA_REGS 32
typedef struct fpa_long {
int fpl_data[2];
} fpa_long; /* 64 bit double presition registers */
/*
* Struct fpa_device defines the control registers in the FPA.
* The base address of this struct is 0xE0000000.
* Since FPA control registers can only be accessed in 32 bit,
* accessing their fields is via "masks" instead of "field".
* E.g., to check the load enable bit of the STATE register, we use
* if (fpa.state & FPA_LOAD_BIT)
* to turn on this bit, we use
* fpa.state |= FPA_LOAD_BIT;
*/
struct fpa_device {
/* 0x000 */
u_char fp_filler1[0x8D0];
/*
* Restore MODE3_0 instr: 1000,1101,0000(8D0) in the address line.
* Data line is u.u_fpa_status.fpas_mode3_0.
*/
u_int fp_restore_mode3_0;
/* 0x8D4 */
u_char fp_filler2[0x84];
/* 0x958, write back address of WSTATUS */
u_int fp_restore_wstatus;
/*
* Turn on unimplemented instr bit in WSTATUS reg: 1001,0101,1100(95C)
* on the address line. Data line is "dont care".
*/
u_int fp_unimplemented;
/* 0x960 */
u_char fp_filler3[0x18];
/*
* Initialize: 1001,0111,1000(978) in the address line.
* Data line is "dont care".
*/
u_int fp_initialize;
/*
* Restore shadow regs: 1001,0111,1100(97C) in the address line.
* Data line is "dont care".
*/
u_int fp_restore_shadow;
/* 0x980 */
u_char fp_filler4[0x280];
/* 0xC00, data reg[0] */
fpa_long fp_data[FPA_NDATA_REGS];
/* 0xD00 */
u_char fp_filler5[0x100];
/* 0xE00, shadow registers */
fpa_long fp_shad[FPA_NSHAD_REGS];
/* 0xE40 */
u_char fp_filler6[0xB8];
/* 0xEF8 */
u_char fp_filler7[0x18];
/* 0xF10, STATE register */
u_int fp_state;
#define FPA_LOAD_BIT 0x80
#define FPA_ACCESS_BIT 0x40
#define FPA_PBITS 0xC0
#define FPA_CONTEXT 0x1F
/* 0xF14, IMASK register */
u_int fp_imask;
#define FPA_INEXACT 0x01
/* 0xF18, LOAD_PTR register */
u_int fp_load_ptr;
#define FPA_RAM_ADDR 0x3FFC
#define FPA_SEG_SELECT 0x03
/*
* Microstore bit segment select, e.g.
* if ((fpa.load_ptr & FPA_SEG_SELECT) == FPA_BIT_71_64)
*/
#define FPA_BIT_71_64 0x00
#define FPA_BIT_63_32 0x01
#define FPA_BIT_31_0 0x02
#define FPA_BIT_23_0 0x03
/* 0xF1C, IERR register */
u_int fp_ierr;
#define FPA_ILLE_CTL_ADDR 0x800000
#define FPA_RETRY 0x400000
#define FPA_HUNG_PIPE 0x200000
#define FPA_ILLEGAL_SEQ 0x100000
#define FPA_EXEC_UCODE 0x080000
#define FPA_ILLEGAL_ACCESS 0x040000
#define FPA_PROTECTION 0x020000
#define FPA_NON32_ACCESS 0x010000
/* 0xF20, PIPE_ACT_INS register */
u_int fp_pipe_act_instr;
/* 0xF24, PIPE_NXT_INS register */
u_int fp_pipe_nxt_instr;
#define FPA_FIRST_V 0x80000000
#define FPA_FIRST_HALF 0x1FFC0000
#define FPA_SECOND_V 0x00008000
#define FPA_SECOND_HALF 0x00001FFC
#define FPA_ADDR_SHIFT 16
/* 0xF28, 0xF2C, 0xF30, 0xF34, PIPE_XXX_DX registers */
u_int fp_pipe_act_d1half;
u_int fp_pipe_act_d2half;
u_int fp_pipe_nxt_d1half;
u_int fp_pipe_nxt_d2half;
/* 0xF38, MODE register */
u_int fp_mode_stable;
#define FPA_WEITEK_MODE 0x0F
/* 0xF3C, WSTATUS register */
u_int fp_wstatus_stable;
#define FPA_WEITEK_ERROR 0x08000
#define FPA_NONEXIST_INSTR 0x04000
#define FPA_STATUS_VALID 0x02000
#define FPA_WEITEK_STATUS 0x00F00
#define FPA_DECODED_STATUS 0x0001F
#define FPA_STATUS_SHIFT 8
/*
* Weitek comparison conditions e.g.
* if ((fpa.wstatus_stable & FPA_DECODED_STATUS) == FPA_LT)
*/
#define FPA_EQ 0x00004
#define FPA_LT 0x00019
#define FPA_GT 0x00000
#define FPA_UNORDERED 0x00002
#define FPA_OTHERS 0x00000
/* 0xF40 */
u_char fp_filler8[0x8];
/* 0xF48, PIPE_STATUS register */
u_int fp_pipe_status;
#define FPA_SECOND_V_NXT 0x800000
#define FPA_FIRST_V_NXT 0x400000
#define FPA_SECOND_V_ACT 0x200000
#define FPA_FIRST_V_ACT 0x100000
#define FPA_IDLE2 0x080000
#define FPA_IDLE1 0x040000
#define FPA_HUNG 0x020000
#define FPA_STABLE 0x010000
/* 0xF4C */
u_char fp_filler9[0x14];
/* 0xF60, READ_REG register */
u_int fp_read_reg;
/* 0xF64, REG_UST_ADDR register */
u_int fp_reg_ust_addr;
#define FPA_MUX_SELECT 0xE0000000
#define FPA_REGRAM_ADDR 0x0FFF0000
#define FPA_USTORE_ADDR 0x00003FFF
/* 0xF68 */
u_char fp_filler10[0x18];
/* 0xF80, hard CLEAR_PIPE register, only used by diagnostic routines */
u_int fp_hard_clear_pipe;
/* 0xF84, CLEAR_PIPE register, used by Unix */
u_int fp_clear_pipe;
/* 0xF88 */
u_char fp_filler11[0x30];
/* 0xFB8, MODE read clear, fields same as fp_mode3_0_stable (0xF38) */
u_int fp_mode3_0_clear;
/* 0xFBC, WSTATUS read clear, fields same as fp_wstatus_stable(0xF3C) */
u_int fp_wstatus_clear;
/* 0xFC0, LD_RAM register */
u_int fp_ld_ram;
} *fpa; /* fpa gets address from fpaprobe() in fpa.c */
#define FPA_MAXLOOP 256

17
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1 i\
/* Define file containing constant name and address (in mapping ram) */
2 i\
/* Contains all constants and coeficients with true addresses (11 bits) */
3 i\
#define SINGLE_CONST 0x400
4 i\
#define DOUBLE_CONST 0x600
5 i\
#define SINGLE_COEF 0x500
6 i\
#define DOUBLE_COEF 0x700
/^[/ * ]/d
s/^\(s.*\) \(.*\) \(.*\)$/#define \1 0x\2+SINGLE_CONST/
s/^\(d.*\) \(.*\) \(.*\)$/#define \1 0x\2+DOUBLE_CONST/
s/^\(c\_s.*\) \(.*\) \(.*\)$/#define \1 0x\2+SINGLE_COEF/
s/^\(c\_d.*\) \(.*\) \(.*\)$/#define \1 0x\2+DOUBLE_COEF/

7
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1 i\
/* Define file containing constant name and address (in mapping ram) */
2 i\
/* Contains all constants accessible to the user with mapped addresses (9 bits) */
/^[/ * ]/d
/^c\_/d
s/^\(.*\) \(.*\) \(.*\)$/#define \1 0x\2/

38
usr.etc/fpa/microcode/ldp.u Normal file
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|*
|* Read Register via the Load Pointer
|*
routine c.rdregmsw r01110100000 lnop ssub
; ; ; recclk; rcsmsw ldptr;
call idle1 cdata;; ; ; ;
routine c.rdreglsw r01110100001 lnop ssub
; ; ; recclk; rcslsw ldptr;
call idle1 cdata;; ; ; ;
|*
|* Write Register via the Load Pointer
|*
routine c.wrregmsw w01110100000 lnop ssub
routine c.wrregrecm w01110100010 lnop ssub
; ; ; ; ldptr;
; ; opdmsw dtor; ; ramwe rcsmsw ldptr;
call idle1; ; dtor; ; ramwe ldptr;
routine c.wrreglsw w01110100001 lnop ssub
routine c.wrregrecl w01110100011 lnop ssub
; ; ; ; ldptr;
; ; opdmsw dtor; ; ramwe rcslsw ldptr;
call idle1; ; dtor; ; ramwe ldptr;
|*
|* Read Ram Location Specified by LOAD_PTR using both
|* halves of the Recovery Register
|*
routine c.rdregrecm r01110100010 lnop ssub
; ; ; recclk; rcsmsw ldptr;
; ; ; recclk; ;
; ; ; recoe recclk;;
; ; ; recoe; ;
call idle1 cdata;; ; ; ;
routine c.rdregrecl r01110100011 lnop ssub
; ; ; recclk; rcslsw ldptr;
; ; ; recclk; ;
; ; ; recoe recclk;;
; ; ; recoe; ;
call idle1 cdata;; ; ; ;

337
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|* @(#)mis.u 1.1 1.1 10/31/94
|*
|* FPA MICROCODE
|* Written by Mark Moyer
|* For modifications, see "FPA MICRO-CODE GUIDE", #800-1870-01
|*
|*
|* Idle 1
|*
; ; ; ; ;
idle1:
map idl1; lmap cslmac; opdsp; recclk; rcssp imm2;
|*
|* Invalid Instructions
|*
|* Shadow Ram Accesses
routine inv.h1 r0111000xxxx lnop ssub
|* Other Register Accesses
routine inv.r1 x01111xxxxxx lnop ssub
|* Register Accesses Via the Load Pointer
routine inv.l1 x011101001xx lnop ssub
routine inv.l2 x01110101xxx lnop ssub
|* NOTE: w0111011111x is Defined as an invalid instruction forever more
|* (it's used in the O.S. to generate the unimplimented status.)
routine inv.l3 x0111011xxxx lnop ssub
|* Single Precision
routine inv.s1 r00xxxxxxxx0 lnop ssub
|* Command
routine inv.c1 r010xxxxxxxx lnop ssub
routine inv.c2 w0101001010x lnop ssub
routine inv.c3 w0101001100x lnop ssub
routine inv.c4 w0101011010x lnop ssub
routine inv.c5 w0101100010x lnop ssub
routine inv.c6 w0101100110x lnop ssub
routine inv.c7 w0101101010x lnop ssub
routine inv.c8 w01011011x0x lnop ssub
routine inv.c9 w0101110110x lnop ssub
routine inv.ca w0101111110x lnop ssub
routine inv.cb w010000101xx lnop ssub
routine inv.cc w01000011xxx lnop ssub
routine inv.cd w0100011011x lnop ssub
routine inv.ce w01000111xxx lnop ssub
routine inv.cf w0100110111x lnop ssub
routine inv.cg1 w01001110000 lnop ssub
routine inv.cg3 w010011101xx lnop ssub
routine inv.cg4 w01001111xxx lnop ssub
routine inv.ch1 w01001011111 lnop ssub
routine inv.ch w0100101110x lnop ssub
routine inv.ci w01001011011 lnop ssub
routine inv.ci2 w0100101100x lnop ssub
routine inv.cj w0100101010x lnop ssub
routine inv.ck w010010100xx lnop ssub
routine inv.cl w0100100xxx0 lnop ssub
routine inv.cm w01001010111 lnop ssub
routine inv.cn w0100001001x lnop ssub
routine inv.stan w01000000100 lnop ssub
routine inv.dtan w01000000101 lnop ssub
routine inv.ssqrt w01000010000 lnop ssub
routine inv.dsqrt w01000010001 lnop ssub
|* Write Weitek Status
routine inv.w1 r0111001xxxx lnop ssub
|* Not Used (some detected by hardware)
routine inv.nu1 x01101xxxxxx lnop ssub
routine inv.nu2 w01110010101 lnop ssub
routine inv.nu3 w01110010110 lnop ssub
routine inv.nu4 w01110010111 lnop ssub
routine inv.nu5 w01110011001 lnop ssub
routine inv.nu6 w01110011010 lnop ssub
routine inv.nu7 w01110011011 lnop ssub
routine inv.nu8 w01110011100 lnop ssub
routine inv.nu9 w01110011101 lnop ssub
routine inv.nua w01110011110 lnop ssub
routine inv.nub w01110011111 lnop ssub
invalid:
; ; ; ; ;
cstat unimpl; ; ; ; ;
hng; ; ; ; ;
call idle1; ; ; ; ;
|* Double Precision
routine inv.d1 r00xxxxxxxx1 lnop ssub
|* Extended
routine inv.x1 r1xxxxxxxxxx lnop ssub
routine inv.x2 w1000xxxxxx1 lnop ssub
routine inv.x3 w10010xxxxx1 lnop ssub
routine inv.x4 w1011xxxxxxx lnop ssub
routine inv.x5 w111011xxxxx lnop ssub
routine inv.x6 w1111xxxxxxx lnop ssub
invalid2:
; ; ; ; ;
jclr clp idl2; ; ; ; ;
cstat unimpl; ; ; ; ;
hng; ; ; ; ;
call idle1; ; ; ; ;
|*
|* General Routines
|*
|* Wait (delay will be (lpreg+1) * 2)
wait:
jloop wait; ; ; ; ;
rtn; ; ; ; ; lpreg-
wait5:
; ; ; ; ;
wait4:
; ; ; ; ;
wait3:
; ; ; ; ;
wait2:
; ; ; ; ;
wait1:
rtn; ; ; ; ;
|*
|* Clear Pipe Clean-up Routines
|* If there is a clear pipe command, the microengine must wait
|* until the current Weitek operation (if any) is completed.
|* The delay must be long enough such that any new operation
|* will not be loaded until the time when the unload is normally
|* done.
|* Must wait 56 instructions
clp56:
; ; ; ; ; lpreg!26
call wait; ; ; ; ;
call idle1; ; ; ; ;
|* Must wait 24 instructions
clp24:
clp20:
; ; ; ; ; lpreg!10
call wait; ; ; ; ;
call idle1; ; ; ; ;
|* Must wait 4 instructions
clp4:
; ; ; ; ;
|* Must wait 3 instructions
clp3:
; ; ; ; ;
clp2:
; ; ; ; ;
|* No operation going on
|* Must wait 1 instructions
clp:
clp1:
call idle1; ; ; ; ;
||*
||* Write Weitek Status Instructions
||*
|routine w.0 w01110010000 lnop ssub
| ; ; ; ; ; ptr5!szero
| ; ; ; ; rcssp ptr5;
| ; lasf scmp0 csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.1 w01110010001 lnop ssub
| ; ; ; ; ; ptr5!smone
| ; ; ; ; rcssp ptr5;
| ; lasf scmp0 csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.2 w01110010010 lnop ssub
| ; ; ; ; ; ptr5!sone
| ; ; ; ; rcssp ptr5;
| ; lasf scmp0 csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.3 w01110010011 lnop ssub
| ; ; ; ; ; ptr5!c_smaxnorm
| ; ; ; ; rcssp ptr5; ptr5!sone
| ; las csla; reg; ; rcssp ptr5;
| ; lbsf ssub csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.4 w01110010100 lnop ssub
| call invalid; ; ; ; ;
|routine w.5 w01110010101 lnop ssub
| ; ; ; ; ; ptr5!c_smaxnorm
| ; ; ; ; rcssp ptr5; ptr5!c_smaxnorm
| ; las csla; reg; ; rcssp ptr5;
| ; lbsf sadd csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.6 w01110010110 lnop ssub
| ; ; ; ; ; ptr5!shalf
| ; ; ; ; rcssp ptr5; ptr5!c_sminnorm
| ; las cslm; reg; ; rcssp ptr5;
| ; lbsf smul cslm; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.7 w01110010111 lnop ssub
| ; ; ; ; ; ptr5!c_sminnorm
| ; ; ; ; rcssp ptr5; ptr5!c_sminnorm
| ; las cslm; reg; ; rcssp ptr5;
| ; lbsf smul cslm; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.8 w01110011000 lnop ssub
| ; ; ; ; ; ptr5!c_sminsub
| ; ; ; ; rcssp ptr5;
| ; lasf scmp0 cslm; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.9 w01110011001 lnop ssub
| ; ; ; ; ; ptr5!szero
| ; ; ; ; rcssp ptr5; ptr5!c_sminsub
| ; las csla; reg; ; rcssp ptr5;
| ; lbsf sadd csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.a w01110011010 lnop ssub
| ; ; ; ; ; ptr5!c_sminsub
| ; ; ; ; rcssp ptr5; ptr5!c_sminsub
| ; las csla; reg; ; rcssp ptr5;
| ; lbsf sadd csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.b w01110011011 lnop ssub
| ; ; ; ; ; ptr5!sone
| ; ; ; ; rcssp ptr5; ptr5!szero
| ; las csla; reg; ; rcssp ptr5;
||# (Note: 12 will cause a delay of 26)
| ; lbsf sdiv csla; reg; ; ; lpreg!12
| call wait; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.c w01110011100 lnop ssub
| ; ; ; ; ; ptr5!c_ssnan
| ; ; ; ; rcssp ptr5; ptr5!szero
| ; las csla; reg; ; rcssp ptr5;
| ; lbsf sadd csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.d w01110011101 lnop ssub
| ; ; ; ; ; ptr5!szero
| ; ; ; ; rcssp ptr5; ptr5!c_ssnan
| ; las csla; reg; ; rcssp ptr5;
| ; lbsf sadd csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.e w01110011110 lnop ssub
| ; ; ; ; ; ptr5!c_ssnan
| ; ; ; ; rcssp ptr5; ptr5!c_ssnan
| ; las csla; reg; ; rcssp ptr5;
| ; lbsf sadd csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|routine w.f w01110011111 lnop ssub
| ; ; ; ; ; ptr5!c_ssnan
| ; ; ; ; rcssp ptr5;
| ; lasf scmp0 csla; reg; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxa; ; ; ;
| ; ; ; ; ;
| call idle1 cstat;woea; ; ; ;
|*
|* Weitek Error Routines
|* Whenever the Weitek chips get an error we hang.
|* For instructions that have written to reg1 we must restore it.
|* For more complicated operations we might have to wait for
|* the other Weitek chip to finish first.
|*
|* This routine is entered in the middle of a write. We play it safe
|* and finish the write cleanly.
|*
|* Double Precision - restore from recovery to ptr2
der2:
; ; ; ; ramwe ptr2;
; ; ; recoe; ramwe rcsmsw ptr2;
; ; ; recoe recclk;ramwe ptr2;
; ; ; recoe; ramwe rcslsw ptr2;
call hang; ; ; recoe; ramwe ptr2;
|* Single Precision - restore from recovery to ptr2
ser2:
; ; ; recclk; ptr2;
; ; ; recoe; ramwe rcssp ptr2;
call hang; ; ; recoe; ramwe ptr2;
|* Double Precision - restore from recovery to ptr1
der1:
; ; ; ; ramwe ptr1;
; ; ; recoe; ramwe rcsmsw ptr1;
; ; ; recoe recclk;ramwe ptr1;
; ; ; recoe; ramwe rcslsw ptr1;
call hang; ; ; recoe; ramwe ptr1;
|* Single Precision - restore from recovery to ptr1
ser1:
; ; ; recclk; ptr1;
; ; ; recoe; ramwe rcssp ptr1;
call hang; ; ; recoe; ramwe ptr1;
|* When we jump here with another jump following immediately,
|* we must do a jump here (hence the jump werr).
prewerr:
jmp werr; ; ; ; ;
werr:
call hang; ; ; ; ;
hang:
hng; ; ; ; ;
; ; ; ; ;
call idle1; ; ; ; ;

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usr.etc/fpa/microcode/reg.u Normal file
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|*
|* Register Accesses
|*
routine reg_read_msw r01100xxxxx0 lnop ssub
cdata; ; ; ; ;
call idle1; ; ; ; ;
routine reg_read_lsw r01100xxxxx1 lnop ssub
; ; ; recclk; rcslsw ptr2;
call idle1 cdata;; ; ; ;
routine reg_write_msw w01100xxxxx0 lnop ssub
routine shadow_write_msw w0111000xxx0 lnop ssub
; ; ; ; ptr2;
; ; opdmsw dtor; ; ramwe rcsmsw ptr2;
call idle1; ; dtor; ; ramwe ptr2;
routine reg_write_lsw w01100xxxxx1 lnop ssub
routine shadow_write_lsw w0111000xxx1 lnop ssub
; ; ; ; ptr2;
; ; opdmsw dtor; ; ramwe rcslsw ptr2;
call idle1; ; dtor; ; ramwe ptr2;

127
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|*
|* Nop Instruction
|*
routine sp.nop w000000xxxx0 lnop sneg
; ; ; ; ;
call idle1; ; ; ; ;
|*
|* Single Precision Negate Instruction
|* Single Precision Absolute Vaulue Instruction
|*
routine sp.neg w000001xxxx0 las sneg
routine sp.abs w000010xxxx0 las sabs
call wait3; lasf fmap csla; opdsp; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woea; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Single Precision Fix Instruction (convert to integer)
|*
routine sp.fix w000100xxxx0 las scvtint
call wait3; lasf scvtint csla; opdsp; ; ;
; csuxa ulsw; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woea; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Single Precision Float Instruction (convert to float)
|*
routine sp.float w000011xxxx0 lal sfloat
call wait3; lalf sfloat csla; opdsp; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woea; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Single Precision Convert Instruction
|*
routine sp.conv w000101xxxx0 las scvtd
call wait3; lasf fmap csla; opdsp; ; ;
; csuxa umsw; ; ; ;
; csuxa ulsw; ; ; ptr2;
jwerr ser2 cstat;woea; dtor; ; ramwe rcsmsw ptr2;
; woea; dtor; ; ramwe rcslsw ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Single Precision Square Instruction
|*
routine sp.sqar w000110xxxx0 las smul
call wait3; lbsf fmap cslm; opdsp; ; ;
; csuxm usp; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woem; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Single Precision Add Instruction
|* Single Precision Subtract Instruction
|*
routine sp.add w000111xxxx0 lbs sadd
routine sp.sub w001000xxxx0 lbs ssub
call wait3; lasf fmap csla; reg; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woea; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Single Precision Multiply Instruction
|*
routine sp.mul w001001xxxx0 las smul
call wait3; lbsf fmap cslm; reg; ; ;
; csuxm usp; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woem; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Single Precision Divide Instruction
|*
routine sp.div w001010xxxx0 lbs sdiv
|# (Note: 12 will cause a delay of 26)
; lasf fmap csla; reg; ; ; lpreg!12
call wait; ; ; ; ;
; ; ; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woea; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Single Precision Backwards Subtract Instruction
|*
routine sp.b.sub w001011xxxx0 las ssub
call wait3; lbsf fmap csla; reg; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woea; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Single Precision Backwards Divide Instruction
|*
routine sp.b.div w001100xxxx0 las sdiv
|# (Note: 12 will cause a delay of 26)
; lbsf fmap csla; reg; ; ; lpreg!12
call wait; ; ; ; ;
; ; ; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr2;
jwerr ser2 cstat;woea; dtor; ; ramwe rcssp ptr2;
call idle1; ; dtor; ; ramwe ptr2;
|*
|* Single Precision Compare With 0
|*
routine sp.eqlzero w001101xxxx0 las scmp0
call wait3; lasf fmap csla; opdsp; ; ;
; csuxa usp; ; ; ;
; ; ; ; ;
jwerr ser2 cstat;woea; ; ; ;
call idle1; ; ; ; ;
|*
|* Single Precision Compare Reg 1 With Operand
|* Single Precision Compare Magnitude Reg 1 With Operand
|*
routine sp.eqlreg1 w001110xxxx0 lbs scmp
routine sp.cmpreg1 w001111xxxx0 lbs scmpm
call wait3; lasf fmap csla; reg; ; ;
; csuxa usp; ; ; ;
; ; ; ; ;
jwerr ser2 cstat;woea; ; ; ;
call idle1; ; ; ; ;

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usr.etc/fpa/microcode/tran.u Normal file
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1576
usr.etc/fpa/microcode/trig.u Normal file
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509
usr.etc/fpa/microcode/xtn.u Normal file
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|*
|* Single Precision Add Instruction
|* Single Precision Subtract Instruction
|*
routine xs.add w100110xxxx0 lbs sadd
routine xs.sub w100111xxxx0 lbs ssub
; lasf fmap csla; reg; ; ;
; ; ; ; ;
; ; ; ; ;
; ; ; ; ;
jclr clp idl2; csuxa usp; ; recclk; rcssp imm2;
; ; ; ; ptr1;
jwerr ser1 cstat;woea; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Double Precision Add Instruction
|* Double Precision Subtract Instruction
|*
routine xd.add w100110xxxx1 lbm dadd
routine xd.sub w100111xxxx1 lbm dsub
; lam csla; reg; ; rcslsw ptr2;
; lal csla; reg; ; ;
jclr clp1 idl2; lblf fmap csla; opdlsw; ; ;
; ; ; recclk; rcsmsw ptr1;
; ; ; recclk; rcslsw ptr1;
xdfin.alu:
; ; ; ; ;
xdfin.alu2:
; csuxa umsw; ; ; ;
; csuxa ulsw; ; ; ptr1;
jwerr der1 cstat;woea; dtor; ; ramwe rcsmsw ptr1;
; woea; dtor; ; ramwe rcslsw ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Single Precision Multiply Instruction
|*
routine xs.mul w101000xxxx0 las smul
call wait3; lbsf fmap cslm; reg; ; ;
jclr clp idl2; csuxm usp; ; recclk; rcssp imm2;
; ; ; ; ptr1;
jwerr ser1 cstat;woem; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Double Precision Multiply Instruction
|*
routine xd.mul w101000xxxx1 lbm dmul
; lam cslm; reg; ; rcslsw ptr2;
; lal cslm; reg; ; ;
jclr clp3 idl2; lblf fmap cslm; opdlsw; ; ;
; ; ; recclk; rcsmsw ptr1;
; ; ; recclk; rcslsw ptr1;
xdfin.mul:
; ; ; ; ;
; ; ; ; ;
; ; ; ; ;
; csuxm umsw; ; ; ;
; csuxm ulsw; ; ; ptr1;
jwerr der1 cstat;woem; dtor; ; ramwe rcsmsw ptr1;
; woem; dtor; ; ramwe rcslsw ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Single Precision Divide Instruction
|*
routine xs.div w101001xxxx0 lbs sdiv
; lasf fmap csla; reg; ; ;
; ; ; ; ;
; ; ; ; ; lpreg!11
jclr clp24 idl2;; ; ; ;
|# (Note: 11 will cause a delay of 24)
call wait; ; ; recclk; rcssp ptr1;
; csuxa usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woea; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Double Precision Divide Instruction
|*
routine xd.div w101001xxxx1 lbm ddiv
; lam csla; reg; ; rcslsw ptr2;
; lal csla; reg; ; ;
jclr clp56 idl2;lblf fmap csla; opdlsw; ; ;
; ; ; recclk; rcsmsw ptr1;
; ; ; recclk; rcslsw ptr1;
|# (Note: 25 will cause a delay of 52)
; ; ; ; ; lpreg!25
call wait; ; ; ; ;
call xdfin.alu2;; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr1;
| jwerr der1 cstat;woea; dtor; ; ramwe rcsmsw ptr1;
| ; woea; dtor; ; ramwe rcslsw ptr1;
| call idle1; ; dtor; ; ramwe ptr1;
|*
|* Single Precision Backwards Subtract Instruction
|*
routine xs.b.sub w101010xxxx0 las ssub
call wait3; lbsf fmap csla; reg; ; ;
jclr clp idl2; csuxa usp; ; recclk; rcssp imm2;
; ; ; ; ptr1;
jwerr ser1 cstat;woea; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Double Precision Backwards Subtract Instruction
|*
routine xd.b.sub w101010xxxx1 lam dsub
; lbm csla; reg; ; rcslsw ptr2;
; lbl csla; reg; ; ;
jclr clp1 idl2; lalf fmap csla; opdlsw; ; ;
; ; ; recclk; rcsmsw ptr1;
call xdfin.alu; ; ; recclk; rcslsw ptr1;
| ; ; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr1;
| jwerr der1 cstat;woea; dtor; ; ramwe rcsmsw ptr1;
| ; woea; dtor; ; ramwe rcslsw ptr1;
| call idle1; ; dtor; ; ramwe ptr1;
|*
|* Single Precision Backwards Divide Instruction
|*
routine xs.b.div w101011xxxx0 las sdiv
; lbsf fmap csla; reg; ; ;
; ; ; ; ;
; ; ; ; ; lpreg!11
jclr clp24 idl2;; ; recclk; rcssp imm2;
|# (Note: 11 will cause a delay of 24)
call wait; ; ; recclk; rcssp ptr1;
; csuxa usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woea; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Double Precision Backwards Divide Instruction
|*
routine xd.b.div w101011xxxx1 lam ddiv
; lbm csla; reg; ; rcslsw ptr2;
; lbl csla; reg; ; ;
jclr clp56 idl2;lalf fmap csla; opdlsw; ; ;
; ; ; recclk; rcsmsw ptr1;
; ; ; recclk; rcslsw ptr1;
|# (Note: 25 will cause a delay of 52)
; ; ; ; ; lpreg!25
call wait; ; ; ; ;
call xdfin.alu2;; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr1;
| jwerr der1 cstat;woea; dtor; ; ramwe rcsmsw ptr1;
| ; woea; dtor; ; ramwe rcslsw ptr1;
| call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Reg 3 +/- (Reg 2 * Operand)
|* Single Precision Instruction
|*
routine xs.r3Ar2Mop w110000xxxx0 las sadd
routine xs.r3Sr2Mop w110001xxxx0 las ssub
call wait3; lbsf smul cslm; reg; ; ;
; csuxm usp; ; ; ;
; ; ; ; ;
jwerr werr cstat;lbs csla woem; ; ; ;
jclr clp2 idl2; ; ; ; rcssp imm3;
call wait3; lasf fmap csla; reg; recclk; rcssp ptr1;
; csuxa usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woea; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Reg 3 +/- (Reg 2 * Operand)
|* Double Precision Instruction
|*
routine xd.r3Ar2Mop w110000xxxx1 lbm dadd
routine xd.r3Sr2Mop w110001xxxx1 lbm dsub
; lam cslm; reg; ; rcslsw ptr2;
; lal cslm; reg; ; ;
jclr clp3 idl2; lblf dmul cslm; opdlsw; ; rcsmsw imm3;
; lam csla; reg; ; rcslsw ptr3;
; lal csla; reg; ; ;
; ; ; recclk; rcsmsw ptr1;
; ; ; recclk; rcslsw ptr1;
; ; ; ; ;
; csuxm umsw; ; ; ;
; csuxm ulsw; ; ; ;
jwerr werr cstat;lbm csla woem; ; ; ;
; lblf fmap csla woem; ; ; ;
; ; ; ; ;
call xdfin.alu; ; ; ; ;
| ; ; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr1;
| jwerr der1 cstat;woea; dtor; ; ramwe rcsmsw ptr1;
| ; woea; dtor; ; ramwe rcslsw ptr1;
| call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- - Reg 3 + (Reg 2 * Operand)
|* Single Precision Instruction
|*
routine xs.Nr3Ar2Mop w110010xxxx0 las ssub
call wait3; lbsf smul cslm; reg; ; ;
; csuxm usp; ; ; ;
; ; ; ; ;
jwerr werr cstat;las csla woem; ; ; ;
jclr clp2 idl2; ; ; ; rcssp imm3;
call wait3; lbsf fmap csla; reg; recclk; rcssp ptr1;
; csuxa usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woea; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- - Reg 3 + (Reg 2 * Operand)
|* Double Precision Instruction
|*
routine xd.Nr3Ar2Mop w110010xxxx1 lbm dsub
; lam cslm; reg; ; rcslsw ptr2;
; lal cslm; reg; ; ;
jclr clp3 idl2; lblf dmul cslm; opdlsw; ; rcsmsw imm3;
; lbm csla; reg; ; rcslsw ptr3;
; lbl csla; reg; ; ;
; ; ; recclk; rcsmsw ptr1;
; ; ; recclk; rcslsw ptr1;
; ; ; ; ;
; csuxm umsw; ; ; ;
; csuxm ulsw; ; ; ;
jwerr werr cstat;lam csla woem; ; ; ;
; lalf fmap csla woem; ; ; ;
; ; ; ; ;
call xdfin.alu; ; ; ; ;
| ; ; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr1;
| jwerr der1 cstat;woea; dtor; ; ramwe rcsmsw ptr1;
| ; woea; dtor; ; ramwe rcslsw ptr1;
| call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Reg 3 * (Reg 2 +/- Operand)
|* Single Precision Instruction
|*
routine xs.r3Mr2Aop w110011xxxx0 lbs sadd
routine xs.r3Mr2Sop w110100xxxx0 lbs ssub
call wait3; lasf fmap csla; reg; ; ;
; csuxa usp; ; ; ;
; ; ; ; ;
jwerr werr cstat;las cslm woea; ; ; ;
jclr clp2 idl2; ; ; ; rcssp imm3;
call wait3; lbsf smul cslm; reg; recclk; rcssp ptr1;
; csuxm usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woem; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Reg 3 * (Reg 2 +/- Operand)
|* Double Precision Instruction
|*
routine xd.r3Mr2Aop w110011xxxx1 lbm dadd
routine xd.r3Mr2Sop w110100xxxx1 lbm dsub
; lam csla; reg; ; rcslsw ptr2;
; lal csla; reg; ; ;
jclr clp3 idl2; lblf fmap csla; opdlsw; ; rcsmsw imm3;
; lam cslm; reg; ; rcslsw ptr3;
; lal cslm; reg; recclk; rcsmsw ptr1;
; ; ; recclk; rcslsw ptr1;
; csuxa ulsw; ; ; ;
; csuxa umsw; ; ; ;
jwerr werr cstat;lblf dmul cslm woea; ; ; ;
; lbm cslm woea; ; ; ;
call xdfin.mul; ; ; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxm umsw; ; ; ;
| ; csuxm ulsw; ; ; ptr1;
| jwerr der1 cstat;woem; dtor; ; ramwe rcsmsw ptr1;
| ; woem; dtor; ; ramwe rcslsw ptr1;
| call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Reg 3 * (- Reg 2 + Operand)
|* Single Precision Instruction
|*
routine xs.r3MNr2Aop w110101xxxx0 las ssub
call wait3; lbsf fmap csla; reg; ; ;
; csuxa usp; ; ; ;
; ; ; ; ;
jwerr werr cstat;las cslm woea; ; ; ;
jclr clp2 idl2; ; ; ; rcssp imm3;
call wait3; lbsf smul cslm; reg; recclk; rcssp ptr1;
; csuxm usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woem; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Reg 3 * (- Reg 2 + Operand)
|* Double Precision Instruction
|*
routine xd.r3MNr2Aop w110101xxxx1 lam dsub
; lbm csla; reg; ; rcslsw ptr2;
; lbl csla; reg; ; ;
jclr clp3 idl2; lalf fmap csla; opdlsw; ; rcsmsw imm3;
; lam cslm; reg; ; rcslsw ptr3;
; lal cslm; reg; recclk; rcsmsw ptr1;
; ; ; recclk; rcslsw ptr1;
; csuxa ulsw; ; ; ;
; csuxa umsw; ; ; ;
jwerr werr cstat;lblf dmul cslm woea; ; ; ;
; lbm cslm woea; ; ; ;
call xdfin.mul; ; ; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxm umsw; ; ; ;
| ; csuxm ulsw; ; ; ptr1;
| jwerr der1 cstat;woem; dtor; ; ramwe rcsmsw ptr1;
| ; woem; dtor; ; ramwe rcslsw ptr1;
| call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Operand * (Reg 3 +/- Reg 2)
|* Single Precision Instruction
|*
routine xs.opMr3Ar2 w111001xxxx0 lnop sadd
routine xs.opMr3Sr2 w111010xxxx0 lnop ssub
; lbs csla; reg; ; ;
jclr clp2 idl2; ; ; ; rcssp imm3;
; lasf fmap csla; reg; recclk; rcssp ptr1;
; ; ; ; ;
; las cslm; opdsp; ; ;
; ; ; ; ;
; csuxa usp; ; ; ;
; ; ; ; ;
jwerr werr cstat;lbsf smul cslm woea; ; ; rcssp ptr1;
call wait2; ; ; ; ;
; csuxm usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woem; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Operand * (Reg 3 +/- Reg 2)
|* Double Precision Instruction
|*
routine xd.opMr3Ar2 w111001xxxx1 lnop dadd
routine xd.opMr3Sr2 w111010xxxx1 lnop dsub
; lbm csla; reg; ; rcslsw ptr2;
; lbl csla; reg; ; ;
jclr clp3 idl2; ; ; ; rcsmsw imm3;
; lam csla; reg; ; rcslsw ptr3;
; lalf fmap csla; reg; ; ;
; lam cslm; opdmsw; ; ;
; lal cslm; opdlsw; ; ;
; ; ; ; ;
; csuxa ulsw; ; ; ;
; csuxa umsw; ; ; ;
jwerr werr cstat;lblf dmul cslm woea; ; ; ;
; lbm cslm woea; ; recclk; rcsmsw ptr1;
call xdfin.mul; ; ; recclk; rcslsw ptr1;
| ; ; ; ; ;
| ; ; ; ; ;
| ; ; ; ; ;
| ; csuxm umsw; ; ; ;
| ; csuxm ulsw; ; ; ptr1;
| jwerr der1 cstat;woem; dtor; ; ramwe rcsmsw ptr1;
| ; woem; dtor; ; ramwe rcslsw ptr1;
| call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Operand +/- (Reg 3 * Reg 2)
|* Single Precision Instruction
|*
routine xs.opAr3Mr2 w110110xxxx0 lnop sadd
routine xs.opSr3Mr2 w110111xxxx0 lnop ssub
; las cslm; reg; ; ;
jclr clp2 idl2; ; ; ; rcssp imm3;
; lbsf smul cslm; reg; recclk; rcssp ptr1;
; ; ; ; ;
; las csla; opdsp; ; ;
; ; ; ; ;
; csuxm usp; ; ; ;
; ; ; ; ;
jwerr werr cstat;lbsf fmap csla woem; ; ; rcssp ptr1;
call wait2; ; ; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woea; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Operand +/- (Reg 3 * Reg 2)
|* Double Precision Instruction
|*
routine xd.opAr3Mr2 w110110xxxx1 lnop dadd
routine xd.opSr3Mr2 w110111xxxx1 lnop dsub
; lam cslm; reg; ; rcslsw ptr2;
; lal cslm; reg; ; ;
jclr clp4 idl2; ; ; ; rcslsw imm3;
; lblf dmul cslm; reg; ; rcsmsw ptr3;
; lbm cslm; reg; ; ;
; lam csla; opdmsw; ; ;
; lal csla; opdlsw; ; ;
; ; ; ; ;
; ; ; recclk; rcsmsw ptr1;
; csuxm umsw; ; recclk; rcslsw ptr1;
; csuxm ulsw; ; ; ;
jwerr werr cstat;lbm csla woem; ; ; ;
; lblf fmap csla woem; ; ; ;
; ; ; ; ;
call xdfin.alu; ; ; ; ;
| ; ; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr1;
| jwerr der1 cstat;woea; dtor; ; ramwe rcsmsw ptr1;
| ; woea; dtor; ; ramwe rcslsw ptr1;
| call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- -Operand + (Reg 3 * Reg 2)
|* Single Precision Instruction
|*
routine xs.NopAr3Mr2 w111000xxxx0 lnop ssub
; las cslm; reg; ; ;
jclr clp2 idl2; ; ; ; rcssp imm3;
; lbsf smul cslm; reg; recclk; rcssp ptr1;
; ; ; ; ;
; lbs csla; opdsp; ; ;
; ; ; ; ;
; csuxm usp; ; ; ;
; ; ; ; ;
jwerr werr cstat;lasf fmap csla woem; ; ; rcssp ptr1;
call wait2; ; ; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woea; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- -Operand + (Reg 3 * Reg 2)
|* Double Precision Instruction
|*
routine xd.NopAr3Mr2 w111000xxxx1 lnop dsub
; lam cslm; reg; ; rcslsw ptr2;
; lal cslm; reg; ; ;
jclr clp4 idl2; ; ; ; rcslsw imm3;
; lblf dmul cslm; reg; ; rcsmsw ptr3;
; lbm cslm; reg; ; ;
; lbm csla; opdmsw; ; ;
; lbl csla; opdlsw; ; ;
; ; ; ; ;
; ; ; recclk; rcsmsw ptr1;
; csuxm umsw; ; recclk; rcslsw ptr1;
; csuxm ulsw; ; ; ;
jwerr werr cstat;lam csla woem; ; ; ;
; lalf fmap csla woem; ; ; ;
; ; ; ; ;
call xdfin.alu; ; ; ; ;
| ; ; ; ; ;
| ; csuxa umsw; ; ; ;
| ; csuxa ulsw; ; ; ptr1;
| jwerr der1 cstat;woea; dtor; ; ramwe rcsmsw ptr1;
| ; woea; dtor; ; ramwe rcslsw ptr1;
| call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Operand2 + (Operand1 * Reg 2)
|* Reg 1 <-- Operand2 - (Operand1 * Reg 2)
|* Single Precision Instruction
|*
routine xs.linpack1 w100000xxxx0 las sadd
routine xs.linpack2 w100001xxxx0 las ssub
call wait3; lbsf smul cslm; reg; ; ;
jclr clp2 idl2; las csla csuxm usp; opdlsw; ; ;
; ; ; recclk; rcssp ptr1;
jwerr werr cstat;lbsf fmap csla woem; ; ; ;
call wait2; ; ; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woea; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- -Operand2 + (Operand1 * Reg 2)
|* Single Precision Instruction
|*
routine xs.linpack3 w100010xxxx0 las ssub
call wait3; lbsf smul cslm; reg; ; ;
jclr clp2 idl2; lbs csla csuxm usp; opdlsw; ; ;
; ; ; recclk; rcssp ptr1;
jwerr werr cstat;lasf fmap csla woem; ; ; ;
call wait2; ; ; ; ;
; csuxa usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woea; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Operand2 * (Operand1 + Reg 2)
|* Reg 1 <-- Operand2 * (Operand1 - Reg 2)
|* Single Precision Instruction
|*
routine xs.linpack4 w100011xxxx0 las sadd
routine xs.linpack6 w100101xxxx0 las ssub
call wait3; lbsf fmap csla; reg; ; ;
jclr clp2 idl2; las cslm csuxa usp; opdlsw; ; ;
; ; ; recclk; rcssp ptr1;
jwerr werr cstat;lbsf smul cslm woea; ; ; ;
call wait2; ; ; ; ;
; csuxm usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woem; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;
|*
|* Reg 1 <-- Operand2 * (-Operand1 + Reg 2)
|* Single Precision Instruction
|*
routine xs.linpack5 w100100xxxx0 lbs ssub
call wait3; lasf fmap csla; reg; ; ;
jclr clp2 idl2; las cslm csuxa usp; opdlsw; ; ;
; ; ; recclk; rcssp ptr1;
jwerr werr cstat;lbsf smul cslm woea; ; ; ;
call wait2; ; ; ; ;
; csuxm usp; ; ; ;
; ; ; ; ptr1;
jwerr ser1 cstat;woem; dtor; ; ramwe rcssp ptr1;
call idle1; ; dtor; ; ramwe ptr1;