611 lines
15 KiB
C
611 lines
15 KiB
C
/* @(#)gtreg.h 1.1 94/10/31 */
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/*
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* Copyright (c) 1990 by Sun Microsystems, Inc.
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*/
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#ifndef _gtreg_h
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#define _gtreg_h
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/*
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* GT graphics accelerator definitions
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*/
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#define RP_BOOT_PROM_OF 0x00000000 /* RP boot PROM */
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#define RP_FE_CTRL_OF 0x00080000 /* FE RP control space */
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#define RP_SU_RAM_OF 0x00084000 /* SU shared RAM */
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#define RP_HOST_CTRL_OF 0x00090000 /* RP host control space */
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#define FBI_PFGO_OF 0x00100000 /* FBI PF copy/fill regs */
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#define FBI_REG_OF 0x00200000 /* FBI PP/PF SS 0/1 regs */
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#define FBO_CLUT_CTRL_OF 0x00300000 /* FBO CLUT control */
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#define FBO_CLUT_MAP_OF 0x00308000 /* FBO CLUT map */
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#define FBO_WLUT_CTRL_OF 0x00310000 /* FBO WLUT control */
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#define FBO_WLUT_MAP_OF 0x00318000 /* FBO WLUT map */
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#define FBO_SCREEN_CTRL_OF 0x00320000 /* FBO programmable regs */
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#define FBO_RAMDAC_CTRL_OF 0x00330000 /* FBO RAMDAC registers */
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#define FE_CTRL_OF 0x00800000 /* FE control space */
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#define FE_HFLAG1_OF 0x00810000 /* FE control flags 1 */
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#define FE_HFLAG2_OF 0x00820000 /* FE control flags 2 */
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#define FE_HFLAG3_OF 0x00830000 /* FE control flags 3 */
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#define FE_I860_OF 0x00840000 /* FE i860 space */
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#define FE_LDM_OF 0x00832000 /* FE LDM */
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#define FB_OF 0x01000000 /* frame buffer */
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#define FB_CD_OF 0x01000000 /* cursor data plane */
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#define FB_CE_OF 0x01080000 /* cursor enable plane */
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#define RP_BOOT_PROM_SZ 0x80000
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#define RP_FE_CTRL_SZ 0x2000
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#define RP_SU_RAM_SZ 0x4000
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#define RP_HOST_CTRL_SZ 0x2000
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#define FBI_PFGO_SZ 0x2000
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#define FBI_REG_SZ 0x2000
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#define FBO_CLUT_CTRL_SZ 0x1000
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#define FBO_CLUT_MAP_SZ 0x8000
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#define FBO_WLUT_CTRL_SZ 0x1000
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#define FBO_WLUT_MAP_SZ 0x2000
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#define FBO_SCREEN_CTRL_SZ 0x1000
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#define FBO_RAMDAC_CTRL_SZ 0x1000
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#define FE_CTRL_SZ 0x2000
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#define FE_HFLAG1_SZ 0x2000
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#define FE_HFLAG2_SZ 0x1000
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#define FE_HFLAG3_SZ 0x1000
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#define FE_I860_SZ 0x2000
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#define FE_LDM_SZ 0x7CE000
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#define FB_SZ 0x1000000
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#define FB_CD_SZ 0x42000
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#define FB_CE_SZ 0x42000
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#define GT_VOFF_BASE 0x0
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#define RP_BOOT_PROM_VA GT_VOFF_BASE
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#define RP_FE_CTRL_VA (RP_BOOT_PROM_VA + RP_BOOT_PROM_SZ)
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#define RP_SU_RAM_VA (RP_FE_CTRL_VA + RP_FE_CTRL_SZ)
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#define RP_HOST_CTRL_VA (RP_SU_RAM_VA + RP_SU_RAM_SZ)
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#define FBI_PFGO_VA (RP_HOST_CTRL_VA + RP_HOST_CTRL_SZ)
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#define FBI_REG_VA (FBI_PFGO_VA + FBI_PFGO_SZ)
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#define FE_I860_VA (FBI_REG_VA + FBI_REG_SZ)
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#define FB_VA (FE_I860_VA + FE_I860_SZ)
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#define FB_CD_VA FB_VA
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#define FB_CE_VA (FB_CD_VA + FB_CD_SZ)
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#define FBO_CLUT_CTRL_VA (FB_VA + FB_SZ)
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#define FBO_CLUT_MAP_VA (FBO_CLUT_CTRL_VA + FBO_CLUT_CTRL_SZ)
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#define FBO_WLUT_CTRL_VA (FBO_CLUT_MAP_VA + FBO_CLUT_MAP_SZ)
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#define FBO_WLUT_MAP_VA (FBO_WLUT_CTRL_VA + FBO_WLUT_CTRL_SZ)
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#define FBO_SCREEN_CTRL_VA (FBO_WLUT_MAP_VA + FBO_WLUT_MAP_SZ)
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#define FBO_RAMDAC_CTRL_VA (FBO_SCREEN_CTRL_VA + FBO_SCREEN_CTRL_SZ)
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#define FE_CTRL_VA (FBO_RAMDAC_CTRL_VA + FBO_RAMDAC_CTRL_SZ)
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#define FE_HFLAG1_VA (FE_CTRL_VA + FE_CTRL_SZ)
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#define FE_HFLAG2_VA (FE_HFLAG1_VA + FE_HFLAG1_SZ)
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#define FE_HFLAG3_VA (FE_HFLAG2_VA + FE_HFLAG2_SZ)
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#define FE_LDM_VA (FE_HFLAG3_VA + FE_HFLAG3_SZ)
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/*
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* LDM definitions
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*/
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#define FE_LDM_START 0xA00000 /* LDM start address */
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#define FE_LDM_END 0xA3FFFC /* LDM end address */
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#define FE_WCS_START 0xE00000 /* WCS start address */
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#define FE_WCS_END 0xFFFFFC /* WCS end address */
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#define FE_LOAD_MASK 0x00ffffff /* Mask for FE Local address */
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#define feaddr2vaddr(x,y) ((x) + ((y) & FE_LOAD_MASK))
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/*
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* mmap defines
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*/
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#define GT_DPORT_VBASE RP_HOST_CTRL_VA
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#define GT_DPORT_MMAPSIZE ((FB_VA+FB_SZ) - GT_DPORT_VBASE)
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#define GT_RP_HOST_VOFFSET (RP_HOST_CTRL_VA - GT_DPORT_VBASE)
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#define GT_FBI_PFGO_VOFFSET (FBI_PFGO_VA - GT_DPORT_VBASE)
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#define GT_FBI_REG_VOFFSET (FBI_REG_VA - GT_DPORT_VBASE)
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#define GT_FE_I860_VOFFSET (FE_I860_VA - GT_DPORT_VBASE)
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#define GT_FB_VOFFSET (FB_VA - GT_DPORT_VBASE)
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#define GT_FB_CD_VOFFSET GT_FB_VOFFSET
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#define GT_FB_CE_VOFFSET (GT_FB_VOFFSET + 0x80000)
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#define GT_FB_BACCESS_VOFFSET (GT_FB_VOFFSET + 0x400000)
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/*
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* GT registers
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*
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* RP host page
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*/
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typedef struct rp_host {
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u_int rp_host_as_reg; /* AS reg */
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u_int rp_host_csr_reg; /* CSR reg */
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} rp_host;
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/*
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* direct port FBI section
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*/
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typedef struct fbi_pfgo {
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u_int fbi_pfgo_copy_dest_addr; /* copy destination addr reg */
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u_int fbi_pfgo_fill_dest_addr; /* fill destination addr reg */
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} fbi_pfgo;
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typedef struct fbi_reg {
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u_int pad0[35];
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u_int fbi_reg_vwclp_x;
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u_int pad1[1];
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u_int fbi_reg_vwclp_y;
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u_int pad2[12];
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u_int fbi_reg_fb_width;
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u_int pad3[5];
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u_int fbi_reg_il_test;
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u_int pad4[72];
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u_int fbi_reg_buf_sel;
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u_int fbi_reg_stereo_cl;
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u_int pad5[125];
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u_int fbi_reg_cur_wid;
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u_int fbi_reg_wid_ctrl;
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u_int fbi_reg_wbc;
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u_int fbi_reg_con_z;
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u_int fbi_reg_z_ctrl;
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u_int fbi_reg_i_wmask;
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u_int fbi_reg_w_wmask;
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u_int fbi_reg_b_mode;
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u_int fbi_reg_b_wmask;
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u_int fbi_reg_rop;
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u_int pad6[3];
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u_int fbi_reg_mpg;
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u_int pad7[498];
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u_int fbi_reg_s_mask;
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u_int fbi_reg_fg_col;
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u_int fbi_reg_bg_col;
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u_int fbi_reg_s_trans;
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u_int fbi_reg_dir_size;
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u_int fbi_reg_copy_src;
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} fbi_reg;
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/*
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* direct port FBO section
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*/
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typedef struct fbo_clut_ctrl {
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u_int clut_csr0;
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u_int clut_csr1;
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} fbo_clut_ctrl;
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#define CLUT8_SIZE 0x100
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#define CLUT24_SIZE 0x100
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#define CLUT12_SIZE 0x4000
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#define WLUT_SIZE 0x1000
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typedef struct H_fbo_clut8 {
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u_int clut8_map[CLUT8_SIZE];
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} H_fbo_clut8;
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typedef struct H_fbo_clut24 {
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u_int clut24_map[CLUT24_SIZE];
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} H_fbo_clut24;
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typedef struct H_fbo_clutfc {
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u_int fcs0;
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u_int fcs1;
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u_int fcs2;
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u_int fcs3;
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} H_fbo_clutfc;
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typedef struct H_fbo_clut16 {
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u_char clut12_map[CLUT12_SIZE];
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} H_fbo_clut12;
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typedef struct fbo_clut_map {
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H_fbo_clut8 fbo_clut8[14];
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H_fbo_clut24 fbo_clut24;
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H_fbo_clutfc fbo_clutfc;
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u_int pad0[252];
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H_fbo_clut12 fbo_clut12;
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} fbo_clut_map;
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typedef struct fbo_wlut_ctrl {
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u_int wlut_csr0;
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u_int wlut_csr1;
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} fbo_wlut_ctrl;
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typedef struct H_fbo_wlut {
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u_char wlut_map[WLUT_SIZE];
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} H_fbo_wlut;
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typedef struct fbo_wlut_map {
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struct H_fbo_wlut fbo_wlut[2];
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} fbo_wlut_map;
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typedef struct fbo_screen_ctrl {
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u_int pad0[8];
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u_int fbo_videomode_0;
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} fbo_screen_ctrl;
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#define SYNC_RUN 0x00000001
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#define VIDEO_ENABLE 0x00000004
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typedef struct fbo_rgb_alpha {
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u_int fbo_rgb_ramdac_addr;
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u_int fbo_rgb_ramdac_gamma;
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u_int fbo_rgb_ramdac_ctrl;
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u_int fbo_rgb_ramdac_cursor;
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u_int fbo_alpha_ramdac_addr;
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u_int fbo_alpha_ramdac_gamma;
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u_int fbo_alpha_ramdac_ctrl;
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u_int fbo_alpha_ramdac_alpha;
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} fbo_rgb_alpha;
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typedef struct fbo_ramdac_map {
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u_int pad0[2];
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u_int ramdac_red;
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u_int pad1[3];
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u_int ramdac_green;
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u_int pad2[3];
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u_int ramdac_blue;
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u_int pad3[1];
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u_int ramdac_addr_reg;
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u_int ramdac_gamma_data_reg;
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u_int pad4[1];
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u_int ramdac_cursor_data_reg;
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} fbo_ramdac_map;
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/*
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* FE registers
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*/
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typedef struct fe_ctrl_sp {
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u_int pad0;
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u_int fe_hcr; /* host communications register */
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u_int fe_imr; /* interface mode register */
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u_int fe_hisr; /* host interrupt status register */
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u_int fe_fisr; /* frontend interrupt status register */
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u_int fe_atu_syncr; /* ATU synchronizing register */
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u_int fe_mdb_syncr; /* MDB synchronizing register */
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u_int fe_hflag_0; /* host flag 0: kernel VCR */
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u_int fe_dflag_0; /* gt flag 0: kernel VCR */
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u_int pad1[2]; /* */
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u_int fe_test_reg; /* test register */
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u_int pad2[1076]; /* */
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u_int fe_par; /* physical address register */
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u_int pad3[127]; /* */
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u_int fe_lvl1index; /* level 1 PTP + index 2 */
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u_int fe_lvl1; /* level 1 PTP */
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} fe_ctrl_sp;
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/*
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* Host Communications Register definitions
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*/
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#define FE_RESET 0x00000001 /* reset the FEP only */
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#define FE_GO 0x00000002 /* allow the GT FEP to run */
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#define FE_ZERO 0x00000020 /* force sequencer to address 0 */
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#define HK_RESET 0x00000040 /* reset to all of the GT */
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#define FREEZE_ACK 0x00000200 /* ATU freeze acknowledge */
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/*
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* Host Interrupt Status Register definitions
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*/
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#define HISR_MSTO 0x80000000 /* master timeout */
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#define HISR_BERR 0x40000000 /* bus error */
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#define HISR_SIZE 0x20000000 /* size error */
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#define HISR_ATU 0x08000000 /* ATU timeout */
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#define HISR_ROOT_INV 0x04000000 /* root pointer not valid */
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#define HISR_LVL1_INV 0x02000000 /* level 1 pointer not valid */
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#define HISR_TLB_MISS 0x01000000 /* persistent TLB miss */
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#define HISR_UVCR 0x00020000 /* user VCR */
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#define HISR_KVCR 0x00010000 /* kernel VCR */
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#define HISR_INTMASK ( HISR_MSTO | \
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HISR_BERR | \
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HISR_SIZE | \
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HISR_ATU | \
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HISR_ROOT_INV | \
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HISR_LVL1_INV | \
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HISR_TLB_MISS | \
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HISR_UVCR | \
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HISR_KVCR \
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)
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#define HISR_EN_MSMERR 0x00008000 /* enable: intr on MSTO/BERR */
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#define HISR_EN_MSSERR 0x00002000 /* intr on SIZE error */
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#define HISR_EN_ATU 0x00000800 /* intr on ATU error */
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#define HISR_EN_UVCR 0x00000002 /* intr on user VCR */
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#define HISR_EN_KVCR 0x00000001 /* intr on kernel VCR */
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#define HISR_ENABMASK ( HISR_EN_MSMERR | \
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HISR_EN_ATU | \
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HISR_EN_UVCR | \
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HISR_EN_KVCR \
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)
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/*
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* ATU Synchronizing register definitions
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*/
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#define ATU_FREEZE 0x00000002 /* freeze any new MSM cycles */
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#define ATU_CLEAR 0x00000001 /* clear the ATU's TLB */
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/*
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* Masks and shifts for forming virtual addresses from the components
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* in the fe_par, fe_rootindex, and fe_lvl1index registers.
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*/
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#define INDX1_MASK 0x00000ffc /* lvl1 index: fe_rootplus[11:2] */
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#define INDX2_MASK 0x00000ffc /* lvl2 index: fe_l1plus[11:2] */
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#define PGOFF_MASK 0x00000fff /* offset: fe_par[11:0] */
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#define INDX1_SHIFT 20 /* lvl1 index left-shifts 20 bits */
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#define INDX2_SHIFT 10 /* lvl2 index left-shifts 10 bits */
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#define GT_PAGESHIFT 12 /* bytes to gt pages */
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typedef struct fe_i860_sp {
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u_int fe_hold;
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u_int pad_0;
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u_int feint_stat;
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u_int pad_1;
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u_int feint_msk;
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u_int pad_2;
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u_int lbdes;
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u_int pad_3;
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u_int lbseg;
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u_int pad_4;
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u_int feds;
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u_int pad_5;
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u_int diagdes;
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u_int pad_6;
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u_int misc_flg;
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u_int pad_7;
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u_int hoint_stat;
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u_int pad_8;
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u_int hoint_msk;
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u_int pad_9;
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u_int itmisc;
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u_int pad_10;
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u_int lb_err_addr;
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} fe_i860_sp;
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/*
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* fe_hold defines
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*/
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#define FE_HOLD 0x1
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#define FE_HLDA 0x2
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/*
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* hoint_stat and hoint_msk define
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*/
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#define FE_LBTO 0x1
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typedef struct fe_page_1 {
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u_int pad0[9];
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u_int fe_hflag_1; /* host flag 1: signal VCR */
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u_int fe_dflag_1; /* gt flag 1: user VCR */
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u_int pad1[1141];
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u_int fe_rootindex; /* root PTP + index 1 */
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u_int fe_rootptp; /* root PTP */
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} fe_page_1;
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#define ROOTVALID 0x00000001 /* root ptp valid bit */
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typedef struct fe_page_2 {
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u_int pad[12];
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u_int fe_hflag_2; /* host flag 2: user VCR */
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u_int fe_dflag_2; /* <unused> */
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} fe_page_2;
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typedef struct fe_page_3 {
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u_int pad[14];
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u_int fe_hflag_3; /* host flag 3: */
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u_int fe_dflag_3;
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} fe_page_3;
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/*
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* GT ioctls
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*/
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struct fb_clutalloc {
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unsigned int index; /* returned CLUT index */
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unsigned int flags; /* CLUT type and flags */
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unsigned int clutindex; /* desired clut */
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};
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/*
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* CLUT types
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*/
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#define CLUT_8BIT 0x1 /* sunview 8 bit CLUT */
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#define CLUT_SHARED 0x2 /* shared CLUT */
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struct fb_clut {
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unsigned int flags; /* flags */
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int index; /* CLUT id */
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int offset; /* offset within the CLUT */
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int count; /* nbr of entries to be posted */
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unsigned char *red; /* pointer to red table */
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unsigned char *green; /* pointer to green table */
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unsigned char *blue; /* pointer to blue table */
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};
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struct fb_fcsalloc {
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int index; /* returned FCS */
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};
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struct fb_vmback {
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caddr_t vm_addr; /* virtual base address */
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int vm_len; /* length (bytes) */
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};
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struct fb_lightpenparam {
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int pen_distance; /* X+Y delta tolerance */
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int pen_time; /* nbr of frames for lightpen undetect */
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};
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struct fb_vmctl {
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u_int vc_function; /* vm function */
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caddr_t vc_addr; /* starting address */
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caddr_t vc_len; /* length (bytes) */
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};
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struct fb_setgamma {
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u_int fbs_flag; /* sets default degamma-or-not state */
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float fbs_gamma; /* the gamma value */
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};
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|
|
|
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|
struct gt_version {
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int gtv_ucode_major;
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int gtv_ucode_minor;
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|
int gtv_ucode_subminor;
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|
u_int gtv_flags;
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|
int gtv_reserved[4];
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|
};
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|
|
|
#define FBV_SUSPEND 0x00000004
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|
#define FBV_RESUME 0x00000008
|
|
|
|
|
|
|
|
/*
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|
* ioctl flags
|
|
*/
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|
#define FB_BLOCK 0x1
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|
#define FB_KERNEL 0x2
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|
#define FB_NO_DEGAMMA 0x4 /* don't degamma 8-bit indexed colors */
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|
#define FB_DEGAMMA 0x8 /* degamma 8-bit indexed colors */
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|
|
|
|
|
/*
|
|
* ioctl definitions
|
|
*/
|
|
#define FB_CLUTALLOC _IOWR(t, 1, struct fb_clutalloc)
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|
#define FB_CLUTFREE _IOW(t, 2, struct fb_clutalloc)
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|
#define FB_CLUTREAD _IOWR(t, 3, struct fb_clut)
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|
#define FB_CLUTPOST _IOW(t, 4, struct fb_clut)
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|
|
|
#define FB_FCSALLOC _IOWR(t, 5, struct fb_fcsalloc)
|
|
#define FB_FCSFREE _IOW(t, 6, struct fb_fcsalloc)
|
|
|
|
#define FB_SETSERVER _IO(t, 7)
|
|
#define FB_SETDIAGMODE _IOW(t, 8, int)
|
|
#define FB_SETWPART _IOW(t, 9, int)
|
|
#define FB_GETWPART _IOR(t, 10, int)
|
|
|
|
#define FB_SETMONITOR _IOW(t, 11, int)
|
|
#define FB_GETMONITOR _IOR(t, 12, int)
|
|
|
|
#define FB_DISCONNECT _IO(t, 16)
|
|
#define FB_LOADKMCB _IOW(t, 17, int)
|
|
#define FB_CONNECT _IOWR(t, 18, struct gt_connect)
|
|
|
|
#define FB_GRABHW _IOR(t, 19, int)
|
|
#define FB_UNGRABHW _IO(t, 20)
|
|
|
|
#define FB_VMBACK _IOW(t, 21, struct fb_vmback)
|
|
#define FB_VMUNBACK _IOW(t, 22, struct fb_vmback)
|
|
|
|
#define FB_SETCLUTPART _IOW(t, 23, int)
|
|
#define FB_GETCLUTPART _IOR(t, 24, int)
|
|
|
|
#define FB_LIGHTPENENABLE _IOW(t, 25, int)
|
|
#define FB_SETLIGHTPENPARAM _IOW(t, 26, struct fb_lightpenparam)
|
|
#define FB_GETLIGHTPENPARAM _IOR(t, 27, struct fb_lightpenparam)
|
|
|
|
#define FB_VMCTL _IOW(t, 30, struct fb_vmctl)
|
|
#define FB_SETGAMMA _IOW(t, 31, struct fb_setgamma)
|
|
#define FB_GETGAMMA _IOR(t, 32, struct fb_setgamma)
|
|
|
|
#define FB_GT_SETVERSION _IOW(t, 40, struct gt_version)
|
|
#define FB_GT_GETVERSION _IOR(t, 41, struct gt_version)
|
|
|
|
|
|
/*
|
|
* defines for fb_wid_item attributes list
|
|
*/
|
|
#define GT_WID_ATTR_MASK_IB 0x00000001
|
|
#define GT_WID_ATTR_MASK_OB 0x00000002
|
|
#define GT_WID_ATTR_MASK_PG 0x00000004
|
|
#define GT_WID_ATTR_MASK_CI 0x00000008
|
|
#define GT_WID_ATTR_MASK_FCS 0x00000010
|
|
|
|
#define GT_WID_ATTR_IMAGE_BUFFER 0
|
|
#define GT_WID_ATTR_OVERLAY_BUFFER 1
|
|
#define GT_WID_ATTR_PLANE_GROUP 2
|
|
#define GT_WID_ATTR_CLUT_INDEX 3
|
|
#define GT_WID_ATTR_FCS 4
|
|
#define GT_WID_TOTAL_ATTR 5
|
|
|
|
|
|
/*
|
|
* defines for CLUTs
|
|
*/
|
|
#define GT_CLUT_INDEX_24BIT 14
|
|
#define GT_CLUT_INDEX_FCS 15
|
|
#define GT_CLUT_INDEX_12BIT 16
|
|
#define GT_CLUT_INDEX_GAMMA 17
|
|
#define GT_CLUT_INDEX_CURSOR 18
|
|
#define GT_CLUT_INDEX_DEGAMMA 19
|
|
|
|
|
|
/*
|
|
* The low-order bit of the minor device number is used to
|
|
* differentiate the accelerator port from the direct port
|
|
*/
|
|
#define GT_ACCEL_PORT 0x1
|
|
|
|
|
|
/*
|
|
* GT monitor types
|
|
*/
|
|
#define GT_MONITOR_TYPE_STANDARD 0x0
|
|
#define GT_MONITOR_TYPE_HDTV 0x1
|
|
#define GT_MONITOR_TYPE_QUAD 0x2
|
|
#define GT_MONITOR_TYPE_STEREO 0x3
|
|
|
|
/*
|
|
* Various monitor configurations
|
|
*/
|
|
#define GT_1280_76 0x0
|
|
#define GT_1280_67 0x1
|
|
#define GT_1152_66 0x2
|
|
#define GT_STEREO 0x3
|
|
#define GT_HDTV 0x4 /* reserved */
|
|
#define GT_NTSC 0x5 /* reserved */
|
|
#define GT_PAL 0x6 /* reserved */
|
|
|
|
|
|
/*
|
|
* Some GT geometry
|
|
*/
|
|
#define GT_NWID 1024
|
|
#define GT_NCLUT 16
|
|
#define GT_NCLUT_8 14
|
|
#define GT_NFCS 4
|
|
#define GT_CMAP_SIZE 256
|
|
|
|
#define GT_PREFETCH_SZ 64
|
|
|
|
#endif _gtreg_h
|