385 lines
13 KiB
C
385 lines
13 KiB
C
/* @(#)tcxreg.h 1.1 94/10/31 SMI */
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/*
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* Copyright 1993, Sun Microsystems, Inc.
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*/
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#ifndef tcxreg_DEFINED
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#define tcxreg_DEFINED
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#define FBTYPE_TCX 21 /* should really be in <sys/fbio.h>, but... */
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/*
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* TCX frame buffer hardware definitions.
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*/
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#define TCX_ROM_SZ (128*1024) /* 2M allocated */
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#define TCX_CMAP_SZ 4096 /* 256k allocated */
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#define TCX_DHC_SZ 4096 /* 256k allocated */
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#define TCX_ALT_SZ 4096 /* 512k allocated */
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#define TCX_THC_SZ 4096 /* 512k allocated */
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#define TCX_TEC_SZ 4096 /* 512k allocated */
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#define TCX_DFB8_SZ (1024*1024) /* 1 meg, 8M allocated */
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#define TCX_DFB24_SZ (4*1024*1024) /* 4 meg, 16M allocated */
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#define TCX_STIP_SZ (8*1024*1024) /* 8 meg, 32M allocated */
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#define TCX_BLIT_SZ (8*1024*1024) /* 8 meg, 32M allocated */
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#define TCX_RDFB32_SZ (4*1024*1024) /* 4 meg, 16M allocated */
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#define TCX_RSTIP_SZ (8*1024*1024) /* 8 meg, 32M allocated */
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#define TCX_RBLIT_SZ (8*1024*1024) /* 8 meg, 32M allocated */
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#define TCX_VRT_SZ 8192
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/*
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* Virtual (mmap offsets) addresses.
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*/
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/* the following constants assume there will never be a tcx larger
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* than 4Kx4K. It would be better to get these from the device
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* driver via an IOCTL, but for now we just hard-wire them.
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*/
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#define TCX_VADDR_DFB8 0 /* up to 16 meg */
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#define TCX_VADDR_DFB24 0x01000000 /* up to 64 meg */
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#define TCX_VADDR_STIP 0x10000000 /* up to 128 meg */
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#define TCX_VADDR_BLIT 0x20000000 /* up to 128 meg */
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#define TCX_VADDR_RDFB32 0x28000000 /* up to 64 meg */
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#define TCX_VADDR_RSTIP 0x30000000 /* up to 128 meg */
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#define TCX_VADDR_RBLIT 0x38000000 /* up to 128 meg */
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#define TCX_VADDR_TEC 0x70000000
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#define TCX_VADDR_CMAP 0x70002000
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#define TCX_VADDR_THC 0x70004000
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#define TCX_VADDR_DHC 0x70008000
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#define TCX_VADDR_ALT 0x7000a000
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#define TCX_VADDR_UART 0x7000c000
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#define TCX_VADDR_VRT 0x7000e000
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#define TCX_VADDR_ROM 0x70010000
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/* number of colormap entries */
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#define TCX_CMAP_ENTRIES 256
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/*
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* TCX capabilities. Info on hardware capability is stored
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* in the struct fbsattr.dev_specific[0], returned by FBIOGATTR.
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*/
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#define TCX_CAP_STIP_ALIGN 0xf /* stipple alignment constraint: */
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#define TCX_CAP_STIP_ALIGN_SH 0 /* 0 to 5 (1,2,4,8,16,32) */
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#define TCX_CAP_C_PLANES 0xf0 /* # control planes, 0-8 */
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#define TCX_CAP_C_PLANES_SH 4
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#define TCX_CAP_BLIT_WIDTH 0xf00 /* max blit width, 2^n (4096 max) */
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#define TCX_CAP_BLIT_WIDTH_SH 8
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#define TCX_CAP_BLIT_HEIGHT 0xf000 /* max blit height, 2^n (4096 max) */
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#define TCX_CAP_BLIT_HEIGHT_SH 12
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#define TCX_CAP_STIP_ROP 0x10000 /* stipple-with-rop supported */
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#define TCX_CAP_BLIT_ROP 0x20000 /* blit-with-rop supported */
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#define TCX_CAP_24_BIT 0x40000 /* 24-bit support */
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#define TCX_CAP_HW_CURSOR 0x80000 /* hardware cursor */
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#define TCX_CAP_PLANE_MASK 0x100000 /* plane mask for 8-bit stipple */
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/* register set id's. Not all TCX's have all register sets. */
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#define TCX_REG_DFB8 0
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#define TCX_REG_DFB24 1
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#define TCX_REG_STIP 2
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#define TCX_REG_BLIT 3
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#define TCX_REG_RDFB32 4
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#define TCX_REG_RSTIP 5
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#define TCX_REG_RBLIT 6
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#define TCX_REG_TEC 7
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#define TCX_REG_CMAP 8
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#define TCX_REG_THC 9
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#define TCX_REG_ROM 10
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#define TCX_REG_DHC 11
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#define TCX_REG_ALT 12
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#define TCX_REG_MAX 13
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/* Physical frame buffer and color map addresses
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* This information is not germane to applications that will call mmap(2);
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* see the TCX_VADDR_* addresses instead.
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*
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* The base address is defined in the configuration file, e.g. GENERIC, or
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* defined by the prom monitor.
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* These constants are the offset from that address.
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*/
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#define TCX_ADDR_ROM 0 /* boot rom */
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#define TCX_ADDR_CMAP 0x0200000 /* colormap */
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#define TCX_ADDR_DHC 0x0240000 /* control registers */
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#define TCX_ADDR_ALT 0x0280000 /* alternate registers */
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#define TCX_ADDR_THC 0x0301000 /* control registers */
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#define TCX_ADDR_TEC 0x0701000 /* control registers */
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#define TCX_ADDR_DFB8 0x0800000 /* 8-bit fb */
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#define TCX_ADDR_DFB24 0x2000000 /* 24-bit fb */
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#define TCX_ADDR_STIP 0x4000000 /* stipple command */
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#define TCX_ADDR_BLIT 0x6000000 /* blit command */
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#define TCX_ADDR_RDFB32 0xa000000 /* raw 32-bit fb */
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#define TCX_ADDR_RSTIP 0xc000000 /* raw stipple */
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#define TCX_ADDR_RBLIT 0xe000000 /* raw blit */
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/* Register definitions */
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/* These offsets are intended to be added to a
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* pointer-to-integer whose value is the base address
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* of the TCX memory mapped register area
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*/
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/* TODO: move these to a seperate file? */
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/* TODO: rename 'tec' to something else? */
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/* Hardware configuration and status */
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#define TCX_TEC_CONFIG ( 0x000 / sizeof(int) )
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#define TCX_TEC_DELAY ( 0x090 / sizeof(int) )
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#define TCX_TEC_STRAPPING ( 0x094 / sizeof(int) )
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#define TCX_TEC_HCMISC ( 0x098 / sizeof(int) )
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#define TCX_TEC_LINECOUNT ( 0x09c / sizeof(int) )
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#define TCX_THC_CONFIG TCX_TEC_CONFIG
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#define TCX_THC_SENSEBUS ( 0x080 / sizeof(int) )
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#define TCX_THC_DELAY TCX_TEC_DELAY
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#define TCX_THC_STRAPPING TCX_TEC_STRAPPING
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#define TCX_THC_HCMISC ( 0x818 / sizeof(int) )
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#define TCX_THC_LINECOUNT TCX_TEC_LINECOUNT
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/* video timing registers */
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#define TCX_TEC_HSS ( 0x0a0 / sizeof(int) )
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#define TCX_TEC_HSE ( 0x0a4 / sizeof(int) )
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#define TCX_TEC_HDS ( 0x0a8 / sizeof(int) )
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#define TCX_TEC_HSEDVS ( 0x0ac / sizeof(int) )
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#define TCX_TEC_HDE ( 0x0b0 / sizeof(int) )
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#define TCX_TEC_VSS ( 0x0c0 / sizeof(int) )
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#define TCX_TEC_VSE ( 0x0c4 / sizeof(int) )
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#define TCX_TEC_VDS ( 0x0c8 / sizeof(int) )
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#define TCX_TEC_VDE ( 0x0cc / sizeof(int) )
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/* cursor control */
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#define TCX_THC_CURSOR_ADDRESS ( 0x8fc / sizeof(int) )
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/* cursor data registers, plane A */
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#define TCX_THC_CURSORA00 ( 0x900 / sizeof(int) )
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#define TCX_THC_CURSORA01 ( 0x904 / sizeof(int) )
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#define TCX_THC_CURSORA02 ( 0x908 / sizeof(int) )
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#define TCX_THC_CURSORA03 ( 0x90c / sizeof(int) )
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#define TCX_THC_CURSORA04 ( 0x910 / sizeof(int) )
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#define TCX_THC_CURSORA05 ( 0x914 / sizeof(int) )
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#define TCX_THC_CURSORA06 ( 0x918 / sizeof(int) )
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#define TCX_THC_CURSORA07 ( 0x91c / sizeof(int) )
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#define TCX_THC_CURSORA08 ( 0x920 / sizeof(int) )
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#define TCX_THC_CURSORA09 ( 0x924 / sizeof(int) )
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#define TCX_THC_CURSORA10 ( 0x928 / sizeof(int) )
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#define TCX_THC_CURSORA11 ( 0x92c / sizeof(int) )
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#define TCX_THC_CURSORA12 ( 0x930 / sizeof(int) )
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#define TCX_THC_CURSORA13 ( 0x934 / sizeof(int) )
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#define TCX_THC_CURSORA14 ( 0x938 / sizeof(int) )
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#define TCX_THC_CURSORA15 ( 0x93c / sizeof(int) )
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#define TCX_THC_CURSORA16 ( 0x940 / sizeof(int) )
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#define TCX_THC_CURSORA17 ( 0x944 / sizeof(int) )
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#define TCX_THC_CURSORA18 ( 0x948 / sizeof(int) )
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#define TCX_THC_CURSORA19 ( 0x94c / sizeof(int) )
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#define TCX_THC_CURSORA20 ( 0x950 / sizeof(int) )
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#define TCX_THC_CURSORA21 ( 0x954 / sizeof(int) )
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#define TCX_THC_CURSORA22 ( 0x958 / sizeof(int) )
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#define TCX_THC_CURSORA23 ( 0x95c / sizeof(int) )
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#define TCX_THC_CURSORA24 ( 0x960 / sizeof(int) )
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#define TCX_THC_CURSORA25 ( 0x964 / sizeof(int) )
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#define TCX_THC_CURSORA26 ( 0x968 / sizeof(int) )
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#define TCX_THC_CURSORA27 ( 0x96c / sizeof(int) )
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#define TCX_THC_CURSORA28 ( 0x970 / sizeof(int) )
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#define TCX_THC_CURSORA29 ( 0x974 / sizeof(int) )
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#define TCX_THC_CURSORA30 ( 0x978 / sizeof(int) )
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#define TCX_THC_CURSORA31 ( 0x97c / sizeof(int) )
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/* cursor data registers, plane B */
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#define TCX_THC_CURSORB00 ( 0x980 / sizeof(int) )
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#define TCX_THC_CURSORB01 ( 0x984 / sizeof(int) )
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#define TCX_THC_CURSORB02 ( 0x988 / sizeof(int) )
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#define TCX_THC_CURSORB03 ( 0x98c / sizeof(int) )
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#define TCX_THC_CURSORB04 ( 0x990 / sizeof(int) )
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#define TCX_THC_CURSORB05 ( 0x994 / sizeof(int) )
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#define TCX_THC_CURSORB06 ( 0x998 / sizeof(int) )
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#define TCX_THC_CURSORB07 ( 0x99c / sizeof(int) )
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#define TCX_THC_CURSORB08 ( 0x9a0 / sizeof(int) )
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#define TCX_THC_CURSORB09 ( 0x9a4 / sizeof(int) )
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#define TCX_THC_CURSORB10 ( 0x9a8 / sizeof(int) )
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#define TCX_THC_CURSORB11 ( 0x9ac / sizeof(int) )
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#define TCX_THC_CURSORB12 ( 0x9b0 / sizeof(int) )
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#define TCX_THC_CURSORB13 ( 0x9b4 / sizeof(int) )
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#define TCX_THC_CURSORB14 ( 0x9b8 / sizeof(int) )
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#define TCX_THC_CURSORB15 ( 0x9bc / sizeof(int) )
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#define TCX_THC_CURSORB16 ( 0x9c0 / sizeof(int) )
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#define TCX_THC_CURSORB17 ( 0x9c4 / sizeof(int) )
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#define TCX_THC_CURSORB18 ( 0x9c8 / sizeof(int) )
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#define TCX_THC_CURSORB19 ( 0x9cc / sizeof(int) )
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#define TCX_THC_CURSORB20 ( 0x9d0 / sizeof(int) )
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#define TCX_THC_CURSORB21 ( 0x9d4 / sizeof(int) )
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#define TCX_THC_CURSORB22 ( 0x9d8 / sizeof(int) )
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#define TCX_THC_CURSORB23 ( 0x9dc / sizeof(int) )
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#define TCX_THC_CURSORB24 ( 0x9e0 / sizeof(int) )
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#define TCX_THC_CURSORB25 ( 0x9e4 / sizeof(int) )
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#define TCX_THC_CURSORB26 ( 0x9e8 / sizeof(int) )
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#define TCX_THC_CURSORB27 ( 0x9ec / sizeof(int) )
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#define TCX_THC_CURSORB28 ( 0x9f0 / sizeof(int) )
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#define TCX_THC_CURSORB29 ( 0x9f4 / sizeof(int) )
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#define TCX_THC_CURSORB30 ( 0x9f8 / sizeof(int) )
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#define TCX_THC_CURSORB31 ( 0x9fc / sizeof(int) )
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/* CONFIG register definitions */
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#define TCX_CONFIG_FBID_SHIFT 28
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#define TCX_CONFIG_FBID 0xf0000000
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#define TCX_CONFIG_SENSE_SHIFT 24
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#define TCX_CONFIG_SENSE 0x7000000
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#define TCX_CONFIG_REV_SHIFT 20
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#define TCX_CONFIG_REV 0xf00000
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#define TCX_CONFIG_RESET_SHIFT 15
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#define TCX_CONFIG_RESET 0x8000
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struct tcx_config {
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unsigned int fbid : 4 ;
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unsigned : 1 ;
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unsigned int sense : 3 ;
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unsigned int rev : 4 ;
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unsigned : 4 ;
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unsigned int reset : 1 ;
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unsigned : 15 ;
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} ;
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/* HCMISC register definitions */
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#define TCX_HCMISC_OPEN_FLAG_SHIFT 31 /* device is open */
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#define TCX_HCMISC_OPEN_FLAG 0x80000000
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#define TCX_HCMISC_EN_SW_ERR_IRQ_SHIFT 29 /* enable SW error interrupt */
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#define TCX_HCMISC_EN_SW_ERR_IRQ 0x20000000
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#define TCX_HCMISC_SW_ERR_SHIFT 28 /* SW error ocurred */
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#define TCX_HCMISC_SW_ERR 0x10000000
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#define TCX_HCMISC_VSYNC_LEVEL_SHIFT 27 /* vsync level when disabled */
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#define TCX_HCMISC_VSYNC_LEVEL 0x8000000
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#define TCX_HCMISC_HSYNC_LEVEL_SHIFT 26 /* hsync level when disabled */
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#define TCX_HCMISC_HSYNC_LEVEL 0x4000000
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#define TCX_HCMISC_DISABLE_VSYNC_SHIFT 25 /* disable v sync */
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#define TCX_HCMISC_DISABLE_VSYNC 0x2000000
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#define TCX_HCMISC_DISABLE_HSYNC_SHIFT 24 /* disable h sync */
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#define TCX_HCMISC_DISABLE_HSYNC 0x1000000
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#define TCX_HCMISC_RESET_SHIFT 12 /* reset */
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#define TCX_HCMISC_RESET 0x1000
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#define TCX_HCMISC_ENABLE_VIDEO_SHIFT 10 /* enable video */
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#define TCX_HCMISC_ENABLE_VIDEO 0x400
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#define TCX_HCMISC_SYNC_SHIFT 9 /* composite sync (ro) */
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#define TCX_HCMISC_SYNC 0x200
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#define TCX_HCMISC_VSYNC_SHIFT 8 /* vertical sync (ro) */
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#define TCX_HCMISC_VSYNC 0x100
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#define TCX_HCMISC_ENABLE_SYNC_SHIFT 7 /* enable sync & video */
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#define TCX_HCMISC_ENABLE_SYNC 0x80
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#define TCX_HCMISC_VBLANK_SHIFT 6 /* vblank in progress (ro) */
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#define TCX_HCMISC_VBLANK 0x40
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#define TCX_HCMISC_EN_IRQ_SHIFT 5 /* enable vert. interrupt */
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#define TCX_HCMISC_EN_IRQ 0x20
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#define TCX_HCMISC_IRQ_SHIFT 4 /* vert. interrupt ocurred */
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#define TCX_HCMISC_IRQ 0x10
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#define TCX_CYCLES_DACWAIT_SHIFT 0 /* mclk between DAC accesses*/
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#define TCX_CYCLES_DACWAIT 0xf
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struct tcx_hcmisc {
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unsigned int sw_err_int_en : 1 ;
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unsigned int sw_err : 1 ;
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unsigned int vsync_level : 1 ;
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unsigned int hsync_level : 1 ;
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unsigned int dis_vsync : 1 ;
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unsigned int dis_hsync : 1 ;
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unsigned : 13 ;
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unsigned int enable_video : 1 ;
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unsigned int sync : 1 ;
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unsigned int vsync : 1 ;
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unsigned int enable_sync : 1 ;
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unsigned int vblank : 1 ;
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unsigned int int_en : 1 ;
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unsigned int intr : 1 ;
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unsigned int cycles_dacwait : 4 ;
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} ;
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/* DELAY register definitions */
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#define TCX_DELAY_SYNC_SHIFT 8
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#define TCX_DELAY_SYNC 0xf00
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#define TCX_DELAY_WR_F_SHIFT 6
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#define TCX_DELAY_WR_F 0xc0
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#define TCX_DELAY_WR_R_SHIFT 4
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#define TCX_DELAY_WR_R 0x30
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#define TCX_DELAY_SOE_F_SHIFT 2
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#define TCX_DELAY_SOE_F 0xc
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#define TCX_DELAY_SOE_S_SHIFT 0
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#define TCX_DELAY_SOE_S 0x3
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struct tcx_delay {
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unsigned : 20 ;
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unsigned int sync : 4 ;
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unsigned int wr_falling : 2 ;
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unsigned int wr_rising : 2 ;
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unsigned int soe_falling : 2 ;
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unsigned int soe_sclk : 2 ;
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} ;
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/* STRAPPING register definitions */
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#define TCX_STRAP_FIFO_LIMIT_SHIFT 20
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#define TCX_STRAP_FIFO_LIMIT 0xf00000
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#define TCX_STRAP_CACHE_EN_SHIFT 16
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#define TCX_STRAP_CACHE_EN 0x10000
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#define TCX_STRAP_ZERO_OFFSET_SHIFT 15
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#define TCX_STRAP_ZERO_OFFSET 0x8000
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#define TCX_STRAP_REFRESH_DIS_SHIFT 14
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#define TCX_STRAP_REFRESH_DIS 0x4000
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#define TCX_STRAP_REF_LOAD_SHIFT 12
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#define TCX_STRAP_REF_LOAD 0x1000
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#define TCX_STRAP_REFRESH_PERIOD_SHIFT 0
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#define TCX_STRAP_REFRESH_PERIOD 0x3ff
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struct tcx_strapping {
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unsigned : 8 ;
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unsigned int fifo_limit : 4 ;
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unsigned : 3 ;
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unsigned int cache_enable : 1 ;
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unsigned int zero_offset : 1 ;
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unsigned int refresh_dis : 1 ;
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unsigned : 1 ;
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unsigned int ref_load : 1 ;
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unsigned : 2 ;
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unsigned int refresh_period : 10 ;
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} ;
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/* CURSOR ADDRESS register definitions */
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#define TCX_CURSOR_ADDR_X_SHIFT 16
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#define TCX_CURSOR_ADDR_X 0xffff0000
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#define TCX_CURSOR_ADDR_Y_SHIFT 0
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#define TCX_CURSOR_ADDR_Y 0xffff
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struct tcx_cursor_address {
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int cursor_x : 16 ;
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int cursor_y : 16 ;
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} ;
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#endif /* tcxreg_DEFINED */
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