265 lines
11 KiB
C
265 lines
11 KiB
C
/*static char fpamfsccsid[] = "@(#)fpa.def.h 1.2 2/28/86 Copyright Sun Microsystems";
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*/
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/*
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* ======================================================
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* defines for FPA register structure
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* ======================================================
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*/
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#define FPA_BASE 0xE0000000
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#define FPA_HANG_DP_1 0xE0000004
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#define MODE_WRITE_REGISTER 0xE00008D0
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#define WSTATUS_WRITE_REGISTER 0xE0000958
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#define LOOP_DIAG_ADDR 0x968
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#define DIAG_INIT_CMD 0xE0000978
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#define REGISTER_ZERO_MSW 0xE0000C00
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#define REGISTER_ZERO_LSW 0xE0000C04
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#define REGISTER_ONE_MSW 0xE0000C08
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#define REGISTER_ONE_LSW 0xE0000C0C
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#define REGISTER_TWO_MSW 0xE0000C10
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#define REGISTER_TWO_LSW 0xE0000C14
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#define REGISTER_THREE_MSW 0xE0000C18
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#define REGISTER_THREE_LSW 0xE0000C1C
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#define REGISTER_FOUR_MSW 0xE0000C20
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#define REGISTER_FOUR_LSW 0xE0000C24
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#define REGISTER_FIVE_MSW 0xE0000C28
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#define REGISTER_FIVE_LSW 0xE0000C2C
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#define REGISTER_SIX_MSW 0xE0000C30
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#define REGISTER_SIX_LSW 0xE0000C34
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#define REGISTER_SEVEN_MSW 0xE0000C38
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#define REGISTER_SEVEN_LSW 0xE0000C3C
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#define REGISTER_EIGHT_MSW 0xE0000C40
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#define REGISTER_EIGHT_LSW 0xE0000C44
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#define REGISTER_NINE_MSW 0xE0000C48
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#define REGISTER_NINE_LSW 0xE0000C4C
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#define REGISTER_TEN_MSW 0xE0000C50
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#define REGISTER_TEN_LSW 0xE0000C54
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#define REGISTER_ELEVEN_MSW 0xE0000C58
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#define REGISTER_ELEVEN_LSW 0xE0000C5C
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#define REGISTER_TWELVE_MSW 0xE0000C60
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#define REGISTER_TWELVE_LSW 0xE0000C64
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#define REGISTER_THIRTEEN_MSW 0xE0000C68
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#define REGISTER_THIRTEEN_LSW 0xE0000C6C
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#define REGISTER_FOURTEEN_MSW 0xE0000C70
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#define REGISTER_FOURTEEN_LSW 0xE0000C74
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#define REGISTER_FIFTEEN_MSW 0xE0000C78
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#define REGISTER_FIFTEEN_LSW 0xE0000C7C
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#define REGISTER_SIXTEEN_MSW 0xE0000C80
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#define REGISTER_SIXTEEN_LSW 0xE0000C84
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#define SHADOW_RAM_START 0xE0000E00
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#define FPA_HANG_DP_2 0xE0001000
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#define FPA_CONTEXT_NUM 0xEC0
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#define FPA_STATE 0xF10
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#define FPA_STATE_ACCENB 0x0040
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/* Regram enable bit - bit 6 */
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/* 0 - disables access to reg ram via pointer */
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/* 1 - enables access */
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#define FPA_STATE_LODENB 0x0080
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/* Load enable bit - bit 7 */
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/* 0 - disables access to microstore */
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/* 1 - enables access to microstore */
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#define FPA_IMASK 0xF14
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#define FPA_IMASK_INXACT 0x0001
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/* inexact error mask - bit 0 */
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/* 0 - errors are disabled */
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/* 1 - errors are enables */
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#define FPA_LOAD_PTR 0xF18
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#define FPA_LOAD_PTR_BITMSK 0x0003
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/* segment select - bits 1:0 */
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/* 00 - bits 71:64 of microstore */
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/* 01 - bits 63:32 of microstore */
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/* 10 - bits 31:0 of microstore */
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/* 11 - bits 23:0 of microstore */
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#define FPA_LOAD_PTR_LOWBIT 0x0000
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#define FPA_LOAD_PTR_MIDBIT 0x0001
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#define FPA_LOAD_PTR_HIGBIT 0x0002
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#define FPA_LOAD_PTR_MAPRAM 0x0003
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#define FPA_LOAD_PTR_ADDMSK 0x3FFC
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/* Ram word addrress - bits 13:2 */
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/* Mapping ram is 4k X 24 bits */
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/* Microstore is 4k X 72 bits */
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/* Register ram 2k X 64 bits */
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#define FPA_LOAD_PTR_UCDMAP 0x8000
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#define FPA_IERR 0xF1C
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#define FPA_ILL_CONACC 0x80
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/* illegal control register address - bit 23 */
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/*#define FPA_RETRY 0x40
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*/ /* 256th retry - bit 22 */
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/*#define FPA_HUNG_PIPE 0x20
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*/ /* hung pipe - pipe access, shadow access, */
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/* control access - bit 21 */
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/*#define FPA_ILLEGAL_SEQ 0x10
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*/ /* Illegal access sequence - bit 20 */
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/*#define FPA_EXEC_UCODE 0x08
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*/ /* attempt to executte via microcode when the */
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/* load enable bit is set - bit 19 */
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/*#define FPA_ILLEGAL_ACCESS 0x04
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*/ /* illegal acces - bit 18 */
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/* reading a write only addrress */
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/* writing a read only address */
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/*#define FPA_PROTECTION 0x02
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*/ /* protection violation - bit 17 */
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/* user write to supervisor space */
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/* attempt to write reg/ram without */
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/* regram-accfess enable bit set */
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/* attempt to access ustore/map ram */
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/* without load enable bit set */
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/* attempt to access illegal address */
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/*#define FPA_NON32_ACCESS 0x01
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*/ /* non - 32 bit access - bit 16 */
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/* **************
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#define FPA_IERR_USRACC 0x0001
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#define FPA_IERR_WRTREG 0x0002
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#define FPA_IERR_WRTUCD 0x0004
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#define FPA_IERR_ILLRED 0x0008
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#define FPA_IERR_ILLWRT 0x0010
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#define FPA_IERR_ILLSEQ 0x0020
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#define FPA_IERR_NON32B 0x0001
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#define FPA_IERR_PARERR 0x0080
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#define FPA_IERR_ILLEXC 0x0100
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#define FPA_IERR_TIMOUT 0x0200
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*****************/
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#define FPA_PIPE_ACT_INS 0xF20
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#define FPA_PIPE_NXT_INS 0xF24
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#define FPA_PIPE_ACT_D1 0xF28
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#define FPA_PIPE_ACT_D2 0xF2C
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#define FPA_PIPE_NXT_D1 0xF30
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#define FPA_PIPE_NXT_D2 0xF34
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/*
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* For PIPE_ACT_INS, PIPE_NXT_INS registers (read only )
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*/
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/*#define FPA_FIRST_V 0x80000000
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*/ /* bits 15 and 31 (V) of these registers */
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/*#define FPA_FIRST_HALF 0x7FFF0000
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*/ /* indicate whether that instruction is valid */
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/*#define FPA_SECOND_V 0x00008000
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*/ /* instruction previously issued by the processor */
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/*#define FPA_SECOND_HALF 0x00007FFF
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*/ /* |V| = 1 instruction was not valid and should */
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/* not be rretransmitted. */
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/* |V| = 0 instruction was valid and should be */
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/* reexecuted or retransmitted. */
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/* Each instruction half is the address to */
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/* which that access was originally */
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/* written (the |V| bit is appended). To retransmit*/
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/* an instruction a PIPE_XXX_Dy */
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/* register is written to the address specified */
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/* by the corresponding half of the */
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/* corresponding PIPE_XXX_INS register. */
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/* This address should be offset by */
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/* 0xE0000000. There is no need to mask off the */
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/* |V| bit because it will be */
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/* ignored by the hardware. */
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#define FPA_MODE3_0S 0xF38
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#define FPA_WSTATUSS 0xF3C
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/***************
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#define FPA_WSTATUS_WTKERR 0x8000
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#define FPA_WSTATUS_PARMSK 0x0F00
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#define FPA_WSTATUS_PARBNK 0x0800
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#define FPA_WSTATUS_WTSTAT 0x0F00
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#define FPA_WSTATUS_WTDCOD 0x001F
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****************/
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/*
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* For WSTATUS Register
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* (register can be read from two address)
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* 1. requires clear pipe before data is returned
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* 2. requires stable pipe only
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*/
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/*#define FPA_WEITEK_ERROR 0x08000
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*/ /* Weitek error (excluding unimpl error) - bit 15 */
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/* 0 - error, 1 - no error */
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/*#define FPA_NONEXIST_INSTR 0x04000
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*/ /* unimplemented instruction - bit 14 */
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/*#define FPA_STATUS_VALID 0x02000
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*/ /* status valid : bit - 13 */
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/* On power up and after a clear pipe tthe */
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/* weitek chip is invalid until this bit is set */
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/* The bit is set every time WSTATUS register is */
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/* updatted by the microcode. */
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/*#define FPA_WEITEK_STATUS 0x00F00
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*/ /* status taken directly from weitek chip - bits 11:8 */
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/*#define FPA_DECODED_STATUS 0x0001F
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*/ /* decoded status : bits 4:0 */
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/*
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* Weitek comparision conditions
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*/
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/*#define FPA_EQ 0x00004 equal */
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/*#define FPA_LT 0x00019 less than */
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/*#define FPA_GT 0x00000 greater than */
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/*#define FPA_UNORDERED 0x00002 unorrdered */
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/*#define FPA_OTHERS 0x00000 for other values */
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#define FPA_PIPE_STATUS 0xF48
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/*
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*
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* For PIPE_STATUS register (read only)
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*
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*/
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/*#define FPA_SECOND_V_NXT 0x80
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*/ /* |V| bit from PIPE_NXT_INS - 2nd half , bit 23 */
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/*#define FPA_FIRST_V_NXT 0x40
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/* /* ditto - 1st half , bit 22 */
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/*#define FPA_SECOND_V_ACT 0x20
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*/ /* |V| bit from PIPE_ACT_INS - 2nd half , bit 21 */
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/*#define FPA_FIRST_V_ACT 0x10
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*/ /* ditto - 1st half , bit 20 */
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/*#define FPA_IDLE2 0x08
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*/ /* idle2 bit from command register , bit 19 */
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/*#define FPA_IDLE1 0x04
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*/ /* idle1 bit from command register , bit 18 */
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/*#define FPA_HUNG_BIT 0x02
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*/ /* hung bit from command register , bit 17 */
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#define FPA_STABLE_BIT 0x01
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/* stable bit - bit 16 */
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/* 0 - pipe may change the state */
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/* 1 - pipe is : */
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/* clear (no pending instructions) */
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/* hung (a Werr has occured) */
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/* waiting for 2nd half of instr */
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#define FPA_CMMND_REG_1 0xF49
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#define FPA_CMMND_REG_2 0xF4A
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#define FPA_CMMND_REG_3 0xF4B
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#define FPA_REG_RAM_ADDR 0xF4D
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#define FPA_READ_REG 0xF60
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#define FPA_UST_ADDR 0xF64
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/*
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* For REG_UST_ADDR register (read only)
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*
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*/
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#define FPA_REGRAM_MUX 0xE0000000
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/* current regram address mux select bits */
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/* (from ustore) , bits 31:29 */
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/*#define FPA_REGRAM_ADDR 0x0FFF0000
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*/ /* current regram address (from mux) - bits 27:16 */
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/*#define FPA_USTORE_ADDR 0x00003FFF
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*/ /* current ustore address (from mux) - bits 13:00 */
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#define FPA_STABLE_PIPE_STATUS 0xF68
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#define FPA_CLR_PIPEHARD 0xF80
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#define FPA_CLEAR_PIPE 0xF84
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#define FPA_MODE3_0C 0xFB8
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#define FPA_WSTATUSC 0xFBC
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#define FPA_LD_RAM 0xFC0
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#define FPA_ID_REG 0xFC1
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