99 lines
4.3 KiB
C
99 lines
4.3 KiB
C
/* static char sccsid[] = "@(#)fpa3x.h 1.1 10/31/94 Copyright Sun Microsystems";*/
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/*
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* ****************************************************************************
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* Source File : fparel.h
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* Original Engr : Nancy Chow
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* Date : 10/11/88
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* Function : This file contains the constant and macro definitions
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* : used by the fparel for fpa-3x.
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* Revision #1 Engr:
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* Date :
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* Change(s) :
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* ****************************************************************************
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*/
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/* ***********
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* Externals
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* ***********/
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extern int dev_no; /* file desc of current context */
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extern int errno; /* system error code */
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extern int no_times; /* test pass count */
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extern int sig_err_flag; /* expect or not expect buserr */
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extern int seg_sig_flag; /* expect or not expect seg violation */
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extern int verbose; /* verbose message display? */
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/* ************
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* Constatnts
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* ************/
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#define FAIL 0
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#define PASS 1
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#define FALSE 0
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#define TRUE 1
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#define FIRST_BIT 0x1 /* initial context bit mask */
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#define MAX_CXTS 32 /* max no. of FPA contexts */
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#define MAX_TEST_CNT 22 /* no. of tests covered */
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#define RAM_LH_FAIL 0xFF /* lower reg ram failure */
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#define RAM_LH_ERR 7 /* lower reg ram failure */
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#define INS_WRMODE 0xE00008D0 /* mode reg write uroutine address */
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#define INS_REGFLP_L 0xE0000E84 /* Register File via LOAD_PTR (least) */
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#define INS_REGFLP_M 0xE0000E80 /* Register File via LOAD_PTR (most) */
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#define REG_IERR 0xE0000F1C /* IERR register address */
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#define REG_IMASK 0xE0000F14 /* IMASK register address */
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#define REG_LDRAM 0xE0000FC0 /* LD_RAM register address */
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#define REG_LOADPTR 0xE0000F18 /* LOAD_PTR register address */
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#define REG_SCLEARPIPE 0xE0000F84 /* soft clear pipe address */
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#define REG_STATE 0xE0000F10 /* STATE register address */
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#define REG_WSTATUS_S 0xE0000F3C /* WSTATUS (stable) register address */
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#define CXT_MASK 0x1F /* mask for context in STATE reg */
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#define IERR_BMASK 0xFF0000 /* mask for IERR bits */
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#define IERR_SHFT 16 /* shift count for IERR bits */
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#define PIPE_HUNG 0x200000 /* IERR pipe hung bit */
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#define NOT_HUNG 1 /* pipe not hung for nack test */
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#define FPA_BUS 2 /* bus error due to FPA error */
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#define BUS_ERR 3 /* bus error */
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#define NONE 0 /* no action */
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#define LOAD_ON 1 /* set Load Enable */
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#define LOAD_OFF 2 /* reset Load Enable */
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#define SEG_SET 3 /* expect segmentation violation */
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#define SEG_RSET 4 /* don't expect seg violation */
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#define SIG_SET 5 /* expect buserror */
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#define SIG_RSET 6 /* don't expect buserror */
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#define VERSION_FPA 0x0 /* version ID for FPA */
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#define VERSION_MASK 0x0E /* mask for FPA version */
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#define MIN_REG_RAM 0 /* min reg ram addr */
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#define MAX_REG_RAM (1024 * 2) /* max reg ram addr */
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#define MIN_MAP_RAM 0 /* min map ram addr */
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#define MAX_MAP_RAM (1024 * 4) /* max map ram addr */
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#define MIN_USTORE (1024 * 4) /* min ustore addr */
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#define MAX_USTORE 16384 /* max ustore addr */
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#define MR_CKSUM_H 0 /* XXX Map Ram MSH checksum */
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#define MR_CKSUM_L 0 /* XXX Map Ram LSH checksum */
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#define UR_CKSUM_H 0 /* XXX Ustore MSH checksum */
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#define UR_CKSUM_L 0 /* XXX Ustore LSH checksum */
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#define CKSUM_XOR 0xBEADFACE /* checksum XOR value */
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#define RR_CKSUM_START 0x400 /* start loc of Reg Ram checksum calc */
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#define RR_CKSUM_END 0x7D0 /* end loc of Reg Ram checksum calc */
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#define CKSUM_LOC 0x7FF /* loc of expected checksum value */
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#define LD_PTR_SHFT 2 /* shift value for LOAD PTR addr */
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#define US_MSH 0 /* most sig half thru LOAD PTR */
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#define US_LSH 1 /* least sig half thru LOAD PTR */
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#define LD_PTR_ADDR(x) (x << LD_PTR_SHFT) /* fill LOAD_PTR addr bits */
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#define LD_PTR_LSH(x) ((x << LD_PTR_SHFT) | US_LSH) /* addr LSH thru LOAD PTR */
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#define LD_PTR_MSH(x) ((x << LD_PTR_SHFT) | US_MSH) /* addr MSH thru LOAD PTR */
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#define INS_REGFC_M(x) (0xE0000C00+(x<<3)) /* Register File context (most) */
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#define INS_REGFC_L(x) (0xE0000C04+(x<<3)) /* Register File context (least) */
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#define SHAD_REG_M(x) (0xE0000E00+(x<<3)) /* Shadow Register (most) */
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#define SHAD_REG_L(x) (0xE0000E04+(x<<3)) /* Shadow Register (least) */
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