129 lines
5.4 KiB
C
129 lines
5.4 KiB
C
/* @(#)bpp_reg.h 1.1 94/10/31 SMI */
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/*
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* Copyright (c) 1990 by Sun Microsystems, Inc.
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*
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* Header file describing the hardware for the
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* bidirectional parallel port
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* driver (bpp) for the Zebra SBus card.
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*
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*/
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#ifndef _sbusdev_bpp_reg_h
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#define _sbusdev_bpp_reg_h
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/* Structure definitions and locals #defines below */
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struct bpp_regs { /* bpp register definitions */
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u_long dma_csr; /* dma control and status register */
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u_long dma_addr; /* Address register. */
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u_long dma_bcnt; /* Byte count register */
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u_long unused; /* to fill the hole */
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u_short hw_config; /* Hardware configuration reg */
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u_short op_config; /* Operation config register */
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u_char data; /* parallel port data */
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u_char trans_cntl; /* transfer control register */
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u_char out_pins; /* output pins register */
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u_char in_pins; /* input pins register */
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u_short int_cntl; /* interrupt control register */
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/* Blame Ira for this misplaced short */
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};
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/* #defines for bits in the dma_csr register */
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#define BPP_INT_PEND 0x00000001 /* pp dma or control intr pending */
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#define BPP_ERR_PEND 0x00000002 /* SBus error pending */
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#define BPP_DRAINING 0x0000000c /* cache is draining */
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#define BPP_INT_EN 0x00000010 /* Enable interrupts */
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#define BPP_FLUSH 0x00000020 /* Flush the cache */
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#define BPP_SLAVE_ERR 0x00000040 /* Slave cycle size error */
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#define BPP_RESET_BPP 0x00000080 /* Hardware reset parallel port */
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#define BPP_READ 0x00000100 /* DMA transfer direction */
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#define BPP_ENABLE_DMA 0x00000200 /* Enable dma transfers */
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#define BPP_ENABLE_BCNT 0x00002000 /* Enable byte counter in dma */
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#define BPP_TERMINAL_CNT 0x00004000 /* Terminal count flag */
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#define BPP_TC_INTR_DISABLE 0x00800000 /* DISABLE terminal count intr */
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#define BPP_EN_CHAIN_DMA 0x01000000 /* Enable chained dma */
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#define BPP_DMA_ON 0x02000000 /* DMA is on */
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#define BPP_ADDR_VALID 0x04000000 /* addr and bcnt are valid */
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#define BPP_NEXT_VALID 0x08000000 /* next addr and bcnt valid */
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#define BPP_DEVICE_ID 0xf0000000 /* device id = 0100 */
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/* #defines for the dma_addr register */
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#define BPP_MAX_DMA 0x01000000 /* 16 MB DMA boundary */
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/* #defines for the hw_config register */
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#define BPP_DSS_MASK 0x007f /* 7-bit DSS value mask */
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#define BPP_DSS_SIZE 0x007f /* 7-bit DSS size mask */
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#define BPP_DSW_MASK 0x7f00 /* 7-bit DSW value mask */
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#define BPP_DSW_SIZE 0x007f /* 7-bit DSW size mask */
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#define BPP_CNTR_TEST 0x8000 /* Allow reading buried counters */
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#define BPP_SEVEN_BITS 0x007f /* mask for allowable DSS, DSW values */
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/* #defines for the op_config register */
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/* WARNING - the EN_VERSATEC bit will disallow lpvi operation */
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#define BPP_EN_VERSATEC 0x0001 /* Enable versatec operation */
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#define BPP_VERSATEC_INTERLOCK 0x0002 /* Versatec connector absent */
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#define BPP_IDLE 0x0008 /* data transfer idle */
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#define BPP_SRST 0x0080 /* reset state machines */
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#define BPP_ACK_OP 0x0100 /* Acknowledge handshake op */
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#define BPP_BUSY_OP 0x0200 /* Busy handshake op */
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#define BPP_EN_DIAG 0x0400 /* Enable diagnostic mode */
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#define BPP_ACK_BIDIR 0x0800 /* Acknowledge is bidirectional */
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#define BPP_BUSY_BIDIR 0x1000 /* Busy is bidirectional */
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#define BPP_DS_BIDIR 0x2000 /* Data Strobe is bidirectional */
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#define BPP_DMA_DATA 0x4000 /* Data value in DMA mem clear */
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#define BPP_EN_MEM_CLR 0x8000 /* Enable DMA memory clear op */
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/* #defines for the trans_cntl register */
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#define BPP_DS_PIN 0x01 /* Data strobe pin */
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#define BPP_ACK_PIN 0x02 /* Acknowledge pin */
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#define BPP_BUSY_PIN 0x04 /* Busy pin (active low) */
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#define BPP_DIRECTION 0x08 /* Direction cntl (0 = write) */
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/*
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* the out_pins register takes the same #defines as the
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* output_reg_pins field of the bpp_pins structure, defined in bpp_io.h.
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* The #defines are included here for reference only.
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*
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* BPP_SLCTIN_PIN 0x01 Select in pin
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* BPP_AFX_PIN 0x02 Auto feed pin
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* BPP_INIT_PIN 0x04 Initialize pin
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* BPP_V1_PIN 0x08 Versatec pin 1
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* BPP_V2_PIN 0x10 Versatec pin 2
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* BPP_V3_PIN 0x20 Versatec pin 3
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*/
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/*
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* the in_pins register takes the same #defines as the
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* input_reg_pins field of the bpp_pins structure, defined in bpp_io.h.
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* The #defines are included here for reference only.
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*
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* BPP_ERR_PIN 0x01 Error pin
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* BPP_SLCT_PIN 0x02 Select pin
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* BPP_PE_PIN 0x04 Paper empty pin
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*/
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/* #defines for the int_cntl register */
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#define BPP_ERR_IRQ_EN 0x0001 /* ERR interrupt enable */
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#define BPP_ERR_IRP 0x0002 /* ERR intr polarity: 1=rising edge */
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#define BPP_SLCT_IRQ_EN 0x0004 /* SLCT interrupt enable */
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#define BPP_SLCT_IRP 0x0008 /* SLCT intr polarity: 1=rising edge */
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#define BPP_PE_IRQ_EN 0x0010 /* PE interrupt enable */
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#define BPP_PE_IRP 0x0020 /* PE intr polarity: 1=rising edge */
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#define BPP_BUSY_IRQ_EN 0x0040 /* BUSY interrupt enable */
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#define BPP_BUSY_IRP 0x0080 /* BUSY intr polarity: 1=rising edge */
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#define BPP_ACK_IRQ_EN 0x0100 /* ACK+ interrupt enable */
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#define BPP_DS_IRQ_EN 0x0200 /* DIR+ interrupt enable */
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#define BPP_ERR_IRQ 0x0400 /* ERR interrupt pending */
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#define BPP_SLCT_IRQ 0x0800 /* SLCT interrupt pending */
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#define BPP_PE_IRQ 0x1000 /* PE interrupt pending */
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#define BPP_BUSY_IRQ 0x2000 /* BUSY interrupt pending */
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#define BPP_ACK_IRQ 0x4000 /* ACK interrupt pending */
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#define BPP_DS_IRQ 0x8000 /* DS interrupt pending */
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#define BPP_ALL_IRQS (BPP_ERR_IRQ | BPP_SLCT_IRQ | BPP_PE_IRQ | \
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BPP_BUSY_IRQ | BPP_ACK_IRQ | BPP_DS_IRQ )
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#endif _sbusdev_bpp_reg_h
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