176 lines
4.7 KiB
C
176 lines
4.7 KiB
C
/* @(#)fdreg.h 1.1 94/10/31 SMI */
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/*
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* Copyright (c) 1989 by Sun Microsystems, Inc.
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*/
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#ifndef _sbusdev_fdreg_h
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#define _sbusdev_fdreg_h
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#define I82077
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/*
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* physical address of the floppy controller on campus
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*/
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#define OBIO_FDC_ADDR 0xF7200000
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#ifdef I82077
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/*
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* types of controllers supported by this driver
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*/
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#define FD_82072 0
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#define FD_82077 1
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#endif I82077
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/*
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* fdc registers
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*/
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#ifdef I82077
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union fdcreg {
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struct {
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u_char fdc_control;
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u_char fdc_fifo;
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} fdc_82072_reg;
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struct fdc_82077_reg {
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u_char fdc_filler1[2];
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u_char fdc_dor; /* Digital Output Register */
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u_char fdc_filler2;
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u_char fdc_control; /* DSR on write, MSR on read */
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#define fdc_msr fdc_control
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#define fdc_dsr fdc_control
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u_char fdc_fifo;
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u_char fdc_filler3;
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u_char fdc_dir; /* Digital Input Register */
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#define fdc_ccr fdc_dir
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} fdc_82077_reg;
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};
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#else
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struct fdcreg {
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u_char fdc_control;
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u_char fdc_fifo;
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};
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#endif I82077
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/* these defines are always the same for 82072 controller chip */
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/* DSR - data rate select register */
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#define SWR 0x80 /* software reset */
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#define PD 0x40 /* power down */
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#define EPL 0x20 /* enable phase lock loop */
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#define PRECOMPMSK 0x1c /* precomp mask */
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#define DRSELMSK 0x3 /* data rate select mask */
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/* MSR - main status register */
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#define RQM 0x80 /* request for master - chip needs attention */
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#define DIO 0x40 /* data in/out - 1 = remove bytes from fifo */
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#define NDM 0x20 /* non-dma mode - 1 during execution phase */
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#define CB 0x10 /* controller busy - command in progress */
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#ifdef I82077
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/* DOR - Digital Output register - 82077 only */
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#define EJECT 0x80 /* eject diskette - replaces bit in auxio reg */
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#define MOTEN 0x10 /* motor enable bit */
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#define DMAGATE 0x8 /* must be high to enable interrupts */
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#define RESET 0x4 /* reset bit - must be 0 to come out of reset state */
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#define DRVSEL 0x3 /* drive select */
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#define ZEROBITS 0x22 /* the rest of the bits should be zero */
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/* DIR - Digital Input register - 82077 only */
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#define DISKCHG 0x80 /* diskette change - replaces bit in auxio reg */
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#endif I82077
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/* DIR - Digital Input register - 82077 only */
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#define DSKCHG 0x80 /* diskette was changed - replaces bit in auxio */
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#ifdef I82077
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#define MOTON_DELAY ((3 * hz) / 4) /* motor on delay 0.75 seconds */
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#define MOTOFF_DELAY (6 * hz) /* motor off delay 6 seconds */
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#endif I82077
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struct fdcmdinfo {
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char *cmdname; /* command name */
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u_char ncmdbytes; /* number of bytes of command */
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u_char nrsltbytes; /* number of bytes in result */
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u_char cmdtype; /* characteristics */
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} fdcmds[] = {
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"", 0, 0, 0, /* - */
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"", 0, 0, 0, /* - */
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"read_track", 9, 7, 1, /* 2 */
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"specify", 3, 0, 3, /* 3 */
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"sense_drv_status", 2, 1, 3, /* 4 */
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"write", 9, 7, 1, /* 5 */
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"read", 9, 7, 1, /* 6 */
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"recalibrate", 2, 0, 2, /* 7 */
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"sense_int_status", 1, 2, 3, /* 8 */
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"write_del", 9, 7, 1, /* 9 */
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"read_id", 2, 7, 2, /* A */
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"motor_on/off", 1, 0, 4, /* B */
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"read_del", 9, 7, 1, /* C */
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"format_track", 10, 7, 1, /* D */
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"dump_reg", 1, 10, 4, /* E */
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"seek", 3, 0, 2, /* F */
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"", 0, 0, 0, /* - */
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"", 0, 0, 0, /* - */
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"", 0, 0, 0, /* - */
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"configure", 4, 0, 4, /* 13 */
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/* relative seek */
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};
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#ifdef NEVER
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XXX add another field so we can look up by command value
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>>> but they are ordered now ??
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XXX maybe need a mask field also?
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XXX add another field / rearrange this for the hwintr's opmode value
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XXX -> YES make these a bit mask
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#endif NEVER
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/* command types */
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#define undefined 0
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#define data_tranfer 1
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#define control_with_int 2
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#define control_without_int 3
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#define new_control 4
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#define GPLN 0x1b /* gap length for read/write command */
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#define GPLF 0x54 /* gap length for format command */
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#define FDATA 0xe5 /* fill data fields during format */
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/* 82072 commands */
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#define MT 0x80
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#define MFM 0x40
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#define SK 0x20
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#define MOT 0x80
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#define DUMPREG 0x0e
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#define CONFIGURE 0x13
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#define SECSIZ512 0x02
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#define SSSDTL 0xff /* special sector size */
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#define NCBRW 0x09 /* number cmd bytes for read/write cmds */
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#define NRBRW 0x07 /* number result bytes for read/write cmds */
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/* 82072 results */
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/* status reg0 */
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#define IC_SR0 0xc0 /* interrupt code */
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#define SE_SR0 0x20 /* seek end */
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#define EC_SR0 0x10 /* equipment check */
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#define NR_SR0 0x08 /* not ready */
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#define H_SR0 0x04 /* head address */
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#define DS_SR0 0x03 /* drive select */
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/* status reg1 */
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#define EN_SR1 0x80 /* end of cylinder */
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#define DE_SR1 0x20 /* data error */
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#define OR_SR1 0x10 /* overrun/underrun */
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#define ND_SR1 0x04 /* no data */
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#define NW_SR1 0x02 /* not writable */
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#define MA_SR1 0x01 /* missing address mark */
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/* status reg3 */
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#define WP_SR3 0x40 /* write protected */
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#define T0_SR3 0x10 /* track zero */
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#endif /* !_sbusdev_fdreg_h */
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