110 lines
2.9 KiB
C
110 lines
2.9 KiB
C
/* @(#)memfb.h 1.1 94/10/31 SMI */
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/*
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* Copyright 1988 by Sun Microsystems, Inc.
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*/
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#ifndef sbus_mem_fb_DEFINED
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#define sbus_mem_fb_DEFINED
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/*
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* Sbus memory frame buffer definitions
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*/
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/* frame buffer address offsets */
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#define MFB_OFF_ID 0 /* ID register/ROM */
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#define MFB_OFF_REG 0x400000 /* video registers */
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#define MFB_OFF_FB 0x800000 /* frame buffer */
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#define MFB_OFF_DUMMY 0xC00000 /* reserved area *
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#define MFB_ID_MASK 0xFFFFFFF0
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#define MFB_ID_VALUE 0xFE010100
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/* colormap (Bt458) */
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struct mfb_cmap {
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u_char addr; /* address register */
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u_char :8, :8, :8;
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u_char cmap; /* color map data register */
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u_char :8, :8, :8;
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u_char ctrl; /* control register */
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u_char :8, :8, :8;
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u_char omap; /* overlay map data register */
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u_char :8, :8, :8;
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};
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/* number of colormap entries */
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#define MFB_CMAP_ENTRIES 256
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/* video registers */
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struct mfb_reg {
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struct mfb_cmap cmap;
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u_char control;
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u_char status;
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u_char cursor_start;
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u_char cursor_end;
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u_char h_blank_set;
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u_char h_blank_clear;
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u_char h_sync_set;
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u_char h_sync_clear;
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u_char comp_sync_clear;
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u_char v_blank_set_high;
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u_char v_blank_set_low;
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u_char v_blank_clear;
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u_char v_sync_set;
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u_char v_sync_clear;
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u_char xfer_holdoff_set;
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u_char xfer_holdoff_clear;
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};
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/* control register bits (read-write) */
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#define MFB_CR_INTEN 0x80 /* interrupt enable */
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#define MFB_CR_VIDEO 0x40 /* video enable */
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#define MFB_CR_MASTER 0x20 /* master timing enable */
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#define MFB_CR_CURSOR 0x10 /* cursor compare enable */
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#define MFB_CR_X0 0x00 /* crystal 0 select */
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#define MFB_CR_X1 0x04 /* crystal 1 select */
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#define MFB_CR_X2 0x08 /* crystal 2 select */
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#define MFB_CR_TEST 0x0C /* test mode */
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#define MFB_CR_DIV1 0x00 /* divide by 1 */
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#define MFB_CR_DIV2 0x01 /* divide by 2 */
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#define MFB_CR_DIV3 0x02 /* divide by 3 */
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#define MFB_CR_DIV4 0x03 /* divide by 4 */
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/* status register bits (read-only, write to clear interrupt) */
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#define MFB_SR_INT 0x80 /* interrupt pending */
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#define MFB_SR_RES_MASK 0x70 /* monitor sense bits */
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#define MFB_SR_1024_768 0x10
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#define MFB_SR_1152_900 0x30
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#define MFB_SR_1280_1024 0x40
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#define MFB_SR_1600_1280 0x50
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#define MFB_SR_ID_MASK 0x0F /* memory mode/board ID bits */
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#define MFB_SR_ID_COLOR 0x01
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#define MFB_SR_ID_MONO 0x02
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#define MFB_SR_ID_MONO_ECL 0x03
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/* set video enable */
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#define mfb_set_video(mp, on) \
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((mp)->control = (mp)->control & ~MFB_CR_VIDEO | \
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((on) ? MFB_CR_VIDEO : 0))
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/* get video enable */
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#define mfb_get_video(mp) ((mp)->control & MFB_CR_VIDEO)
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/* interrupt enable */
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#define mfb_int_enable(mp) ((mp)->control |= MFB_CR_INTEN)
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/* interrupt disable */
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#define mfb_int_disable(mp) \
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((mp)->control &= ~MFB_CR_INTEN, (mp)->status = 0)
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/* is interrupt pending? */
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#define mfb_int_pending(mp) ((mp)->status & MFB_SR_INT)
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/* mmap offset for registers (superuser only) */
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#define MFB_REG_MMAP_OFFSET 0x10000000
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#endif !sbus_mem_fb_DEFINED
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