196 lines
5.3 KiB
C
196 lines
5.3 KiB
C
/*
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* @(#) mmcodec_reg.h 1.1@(#) Copyright (c) 1991-92 Sun Microsystems, Inc.
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*/
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/*
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* MMCODEC - Multi-Media Codec operates over the CHI bus and interfaces
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* with DBRI.
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*/
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#ifndef _sbusdev_mmcodec_reg_h
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#define _sbusdev_mmcodec_reg_h
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/* Data Mode timeslot structure */
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typedef union {
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struct {
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/* time slot 5 */
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unsigned char
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om1:1, /* analog output line 1 control */
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om0:1, /* output line 0 control */
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lo:6; /* left channel output attenuation */
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/* time slot 6 */
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unsigned char
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:1,
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sm:1, /* speaker mute */
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ro:6; /* right channel output attenuation */
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/* time slot 7 */
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unsigned char
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pio:2, /* parallel input/output bits */
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ovr:1, /* overrange */
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is:1, /* line/microphone input selection */
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lg:4; /* left channel input gain */
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/* time slot 8 */
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unsigned char
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ma:4, /* monitor attenutation */
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rg:4; /* right channel input gain */
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} r;
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unsigned short word16[2]; /* short-word access */
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unsigned int word32; /* word access */
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} mmcodec_data_t;
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/* Time Slot 5 data mode bit defines */
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#define MMCODEC_OM0_ENABLE 0x1 /* Output Line 0 On */
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#define MMCODEC_OM1_ENABLE 0x1 /* Output Line 1 On */
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#define MMCODEC_MIN_ATEN (0) /* minimum attenuation */
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#define MMCODEC_MAX_ATEN (31) /* maximum usable attenuation */
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#define MMCODEC_MAX_DEV_ATEN (63) /* maximum device attenuation */
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/* Time Slot 6 data mode bit defines */
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#define MMCODEC_SM 0x1 /* 1 is enabled, 0 is muted */
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/* Time Slot 7 data mode bit defines */
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#define MMCODEC_OVR_CLR 0x0 /* Clear ovr condition (wt) */
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#define MMCODEC_OVR 0x1 /* Overrange occurred (rd) */
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#define MMCODEC_IS_LINE 0x0 /* Line level input select */
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#define MMCODEC_IS_MIC 0x1 /* Microphone input select */
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#define MMCODEC_MIN_GAIN (0)
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#define MMCODEC_MAX_GAIN (15)
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/* Time Slot 8 data mode bit defines */
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#define MMCODEC_MA_MIN_ATEN (0)
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#define MMCODEC_MA_MAX_ATEN (15)
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/* Control Mode timeslot structure */
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typedef union {
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struct {
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/* time slot 1 */
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unsigned char
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:4,
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vs1:1, /* Vendor Specific bit */
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dcb:1, /* Data control handshake bit */
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sre:1, /* Shadow register enable */
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vs0:1; /* Vendor Specific bit */
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/* time slot 2 */
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unsigned char
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:2,
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dfr:3, /* Data conversion frequency */
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st:1, /* Stereo bit */
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df:2; /* Data format selection */
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/* time slot 3 */
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unsigned char
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:2,
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mck:2, /* Clock source select */
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bsel:2, /* Bit rate select */
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xclk:1, /* Transmit clock select */
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xen:1; /* Transmitter enable */
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/* time slot 4 */
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unsigned char
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:6,
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enl:1, /* Enable loopback testing */
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adl:1; /* Analog/Digital loopback */
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/* time slot 5 */
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unsigned char
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pio:2, /* Parallel input/output lines */
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:6;
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/* time slot 6 */
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unsigned char
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:8; /* reserved */
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/* time slot 7 */
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unsigned char
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manufacturer:4, /* Manufacturer identification */
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revision:4; /* Revision level of Codec */
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/* time slot 8 */
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unsigned char
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:8; /* reserved */
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} r;
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unsigned short word16[4]; /* short-word access */
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unsigned int word32[2]; /* word access */
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} mmcodec_ctrl_t;
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/* Time Slot 1 control mode bit defines */
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#define MMCODEC_DCB 0x1 /* Data control handshake */
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#define MMCODEC_SRE 0x1 /* Shadow register enable */
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#define MMCODEC_VS0 0x0
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#define MMCODEC_VS1 0x1
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/* Time Slot 2 data frequency rate bit defines */
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#define MMCODEC_DFR_8000 0x0
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#define MMCODEC_DFR_5513 0x0
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#define MMCODEC_DFR_16000 0x1
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#define MMCODEC_DFR_11025 0x1
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#define MMCODEC_DFR_27429 0x2
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#define MMCODEC_DFR_18900 0x2
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#define MMCODEC_DFR_32000 0x3
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#define MMCODEC_DFR_22050 0x3
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#define MMCODEC_DFR_37800 0x4
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#define MMCODEC_DFR_44100 0x5
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#define MMCODEC_DFR_48000 0x6
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#define MMCODEC_DFR_33075 0x6
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#define MMCODEC_DFR_9600 0x7
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#define MMCODEC_DFR_6615 0x7
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#define MMCODEC_ST_MONO 0x0 /* Mono mode */
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#define MMCODEC_ST_STEREO 0x1 /* Stereo mode */
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#define MMCODEC_DF_16_BIT 0x0 /* Data format 16 bit linear */
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#define MMCODEC_DF_ULAW 0x1 /* Data format 8 bit u-law */
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#define MMCODEC_DF_ALAW 0x2 /* Data format 8 bit A-law */
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/* Time Slot 3 master clock bit defines */
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#define MMCODEC_MCK_MSTR 0x0 /* SCLK is master clock */
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#define MMCODEC_MCK_XTAL1 0x1 /* Crystal 1 24.576 MHz */
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#define MMCODEC_MCK_XTAL2 0x2 /* Crystal 2 16.9344 MHz */
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#define MMCODEC_MCK_EXT 0x3 /* External clock source */
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#define MMCODEC_BSEL_64 0x0 /* 64 bits per frame */
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#define MMCODEC_BSEL_128 0x1 /* 128 bits per frame */
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#define MMCODEC_BSEL_256 0x2 /* 256 bits per frame */
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#define MMCODEC_XCLK 0x1 /* Xmit clock and frame sync */
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#define MMCODEC_XEN 0x0 /* enable serial data output */
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/* Time Slot 4 loopback bit defines */
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#define MMCODEC_ENL 0x1 /* Enable loopback testing */
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#define MMCODEC_ADL_DIG 0x0 /* Digital loopback mode */
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#define MMCODEC_ADL_ANLG 0x1 /* Analog loopback mode */
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/* General MMCODEC defines */
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#define MMCODEC_LEN 256 /* 256 bits/frame */
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/* XXX - This potentially belongs in something like dbri_sun_chi.h or ... */
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#define SCHI_SET_DATA_MODE DBRI_PIO_3
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#define SCHI_SET_CTRL_MODE (0 << 3)
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#define SCHI_SET_INT_PDN DBRI_PIO_2
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#define SCHI_CLR_INT_PDN (0 << 2)
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#define SCHI_SET_RESET (0 << 1)
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#define SCHI_CLR_RESET DBRI_PIO_1
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#define SCHI_SET_PDN DBRI_PIO_0
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#define SCHI_CLR_PDN (0 << 0)
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#define SCHI_ENA_MODE DBRI_PIO3_EN
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#define SCHI_ENA_INT_PDN DBRI_PIO2_EN
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#define SCHI_ENA_RESET DBRI_PIO1_EN
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#define SCHI_ENA_PDN DBRI_PIO0_EN
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#define SCHI_ENA_ALL (0xF0)
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#endif /* !_sbusdev_mmcodec_reg_h */
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