139 lines
4.3 KiB
C
139 lines
4.3 KiB
C
/* @(#)ncrsbc.h 1.1 94/10/31 SMI */
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/*
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* Copyright (c) 1989 by Sun Microsystems, Inc.
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*/
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#ifndef _scsi_adapters_ncrsbc_h
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#define _scsi_adapters_ncrsbc_h
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/*
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* NCR 5380 SBC (SCSI Bus Controller) Registers.
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*/
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struct ncrsbc {
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u_char cdr; /* R: current data register */
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#define odr cdr /* W: output data register */
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u_char icr; /* RW: initiator command register */
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u_char mr; /* RW: mode register */
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u_char tcr; /* RW: target command register */
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u_char cbsr; /* R: current bus status register */
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#define ser cbsr /* W: select/reselect enable register */
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u_char bsr; /* R: bus and status register */
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#define send bsr /* W: start dma for tgt/initiator send xfer */
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u_char idr; /* R: input data register */
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#define trcv idr /* W: start dma for target receive transfer */
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u_char clr; /* R: read to clear parity error, */
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/* interrupt request, and busy */
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/* failure bits in the bsr */
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#define ircv clr /* W: start dma for initiator rcv transfer */
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};
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/*
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* bits in the sbc initiator command register
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*/
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#define NCR_ICR_RST 0x80 /* (r/w) assert reset */
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#define NCR_ICR_AIP 0x40 /* (r) arbitration in progress */
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#define NCR_ICR_TEST 0x40 /* (w) test mode, disables output */
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#define NCR_ICR_LA 0x20 /* (r) lost arbitration */
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#define NCR_ICR_DE 0x20 /* (w) differential enable */
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#define NCR_ICR_ACK 0x10 /* (r/w) assert acknowledge */
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#define NCR_ICR_BUSY 0x08 /* (r/w) assert busy */
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#define NCR_ICR_SEL 0x04 /* (r/w) assert select */
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#define NCR_ICR_ATN 0x02 /* (r/w) assert attention */
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#define NCR_ICR_DATA 0x01 /* (r/w) assert data bus */
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#define ICR_BITS "\20\10RST\7AIP\6LA\5ACK\4BSY\3SEL\2ATN\1DATA"
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/*
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* bits in the sbc mode register (same on read or write)
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*/
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#define NCR_MR_BDMA 0x80 /* block mode dma */
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#define NCR_MR_TRG 0x40 /* target mode */
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#define NCR_MR_EPC 0x20 /* enable parity check */
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#define NCR_MR_EPI 0x10 /* enable parity interrupt */
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#define NCR_MR_EEI 0x08 /* enable eop interrupt */
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#define NCR_MR_MBSY 0x04 /* monitor busy */
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#define NCR_MR_DMA 0x02 /* dma mode */
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#define NCR_MR_ARB 0x01 /* arbitration mode */
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#define MR_BITS "\20\2DMA\1ARB"
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/*
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* bits in the sbc target command register
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*/
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#define NCR_TCR_LAST 0x80 /* Last byte sent */ /* for 53C80 only */
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#define NCR_TCR_REQ 0x08 /* assert request */
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#define NCR_TCR_MSG 0x04 /* assert message */
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#define NCR_TCR_CD 0x02 /* assert command/data */
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#define NCR_TCR_IO 0x01 /* assert input/output */
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#define TCR_BITS "\20\10LAST\4REQ\3MSG\2CD\1IO"
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/*
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* settings of tcr to reflect different information transfer phases
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*/
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#define TCR_COMMAND (NCR_TCR_CD)
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#define TCR_MSG_OUT (NCR_TCR_MSG | NCR_TCR_CD)
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#define TCR_DATA_OUT 0
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#define TCR_STATUS (NCR_TCR_CD | NCR_TCR_IO)
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#define TCR_MSG_IN (NCR_TCR_MSG | NCR_TCR_CD | NCR_TCR_IO)
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#define TCR_DATA_IN (NCR_TCR_IO)
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/*
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* This is actually an illegal phase- we use it to keep the ncr
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* chip from recognizing a phase on the bus
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*/
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#define TCR_UNSPECIFIED (NCR_TCR_MSG)
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/*
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* bits in the sbc current bus status register
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*/
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#define NCR_CBSR_RST 0x80 /* reset */
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#define NCR_CBSR_BSY 0x40 /* busy */
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#define NCR_CBSR_REQ 0x20 /* request */
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#define NCR_CBSR_MSG 0x10 /* message */
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#define NCR_CBSR_CD 0x08 /* command/data */
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#define NCR_CBSR_IO 0x04 /* input/output */
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#define NCR_CBSR_SEL 0x02 /* select */
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#define NCR_CBSR_DBP 0x01 /* data bus parity */
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#define NCR_CBSR_RESEL (NCR_CBSR_SEL | NCR_CBSR_IO)
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#define CBSR_BITS "\20\10RST\7BSY\6REQ\5MSG\4CD\3IO\2SEL\1DBP"
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/*
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* scsi bus signals reflecting different information transfer phases
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*/
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#define CBSR_PHASE_BITS (NCR_CBSR_CD | NCR_CBSR_MSG | NCR_CBSR_IO)
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#define PHASE_COMMAND (NCR_CBSR_CD)
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#define PHASE_MSG_OUT (NCR_CBSR_MSG | NCR_CBSR_CD)
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#define PHASE_DATA_OUT 0
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#define PHASE_STATUS (NCR_CBSR_CD | NCR_CBSR_IO)
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#define PHASE_MSG_IN (NCR_CBSR_MSG | NCR_CBSR_CD | NCR_CBSR_IO)
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#define PHASE_DATA_IN (NCR_CBSR_IO)
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/*
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* bits in the sbc bus and status register
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*/
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#define NCR_BSR_EDMA 0x80 /* end of dma */
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#define NCR_BSR_RDMA 0x40 /* dma request */
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#define NCR_BSR_PERR 0x20 /* parity error */
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#define NCR_BSR_INTR 0x10 /* interrupt request */
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#define NCR_BSR_PMTCH 0x08 /* phase match */
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#define NCR_BSR_BERR 0x04 /* busy error */
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#define NCR_BSR_ATN 0x02 /* attention */
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#define NCR_BSR_ACK 0x01 /* acknowledge */
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#define BSR_BITS "\20\6PERR\5INTR\4PMTCH\3BERR\2ATN\1ACK"
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#endif /* !_scsi_adapters_ncrsbc_h */
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