99 lines
3.1 KiB
C
99 lines
3.1 KiB
C
/* @(#)udc.h 1.1 94/10/31 SMI */
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/*
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* Copyright (c) 1989 by Sun Microsystems, Inc.
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*/
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#ifndef _scsi_adapters_udc_h
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#define _scsi_adapters_udc_h
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/*
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* AMD 9516 UDC (Universal DMA Controller) Registers.
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*
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* Used for the Sun3/50 and Sun3/60 SCSI interfaces only.
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*/
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/*
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* addresses of the udc registers accessed directly by driver
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*/
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#define UDC_ADR_MODE 0x38 /* master mode register */
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#define UDC_ADR_COMMAND 0x2e /* command register (write only) */
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#define UDC_ADR_STATUS 0x2e /* status register (read only) */
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#define UDC_ADR_CAR_HIGH 0x26 /* chain addr reg, high word */
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#define UDC_ADR_CAR_LOW 0x22 /* chain addr reg, low word */
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#define UDC_ADR_CARA_HIGH 0x1a /* cur addr reg A, high word */
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#define UDC_ADR_CARA_LOW 0x0a /* cur addr reg A, low word */
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#define UDC_ADR_CARB_HIGH 0x12 /* cur addr reg B, high word */
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#define UDC_ADR_CARB_LOW 0x02 /* cur addr reg B, low word */
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#define UDC_ADR_CMR_HIGH 0x56 /* channel mode reg, high word */
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#define UDC_ADR_CMR_LOW 0x52 /* channel mode reg, low word */
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#define UDC_ADR_COUNT 0x32 /* number of words to transfer */
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/*
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* For a dma transfer, the appropriate udc registers are loaded from a
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* table in memory pointed to by the chain address register.
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*/
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struct udc_table {
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u_short rsel; /* tells udc which regs to load */
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u_short haddr; /* high word of main mem dma address */
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u_short laddr; /* low word of main mem dma address */
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u_short count; /* num words to transfer */
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u_short hcmr; /* high word of channel mode reg */
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u_short lcmr; /* low word of channel mode reg */
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};
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/*
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* indicates which udc registers are to be set based on info in above table
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*/
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#define UDC_RSEL_RECV 0x0182
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#define UDC_RSEL_SEND 0x0282
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/*
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* setting of chain mode reg: selects how the dma op is to be executed
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*/
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#define UDC_CMR_HIGH 0x0040 /* high word of channel mode reg */
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#define UDC_CMR_LSEND 0x00c2 /* low word of cmr when send */
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#define UDC_CMR_LRECV 0x00d2 /* low word of cmr when receiving */
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/*
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* setting for the master mode register
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*/
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#define UDC_MODE 0xd /* enables udc chip */
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/*
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* setting for the low byte in the high word of an address
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*/
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#define UDC_ADDR_INFO 0x40 /* inc addr after each word is dma'd */
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/*
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* udc commands
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*/
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#define UDC_CMD_STRT_CHN 0xa0 /* start chaining */
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#define UDC_CMD_CIE 0x32 /* channel 1 interrupt enable */
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#define UDC_CMD_RESET 0x00 /* reset udc, same as hdw reset */
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/*
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* bits in the udc status register
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*/
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#define UDC_SR_CIE 0x8000 /* channel interrupt enable */
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#define UDC_SR_IP 0x2000 /* interrupt pending */
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#define UDC_SR_CA 0x1000 /* channel abort */
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#define UDC_SR_NAC 0x0800 /* no auto reload or chaining*/
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#define UDC_SR_WFB 0x0400 /* waiting for bus */
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#define UDC_SR_NCRP 0x0200 /* second interrupt pending */
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#define UDC_SR_HM 0x0040 /* hardware mask */
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#define UDC_SR_HRQ 0x0020 /* hardware request */
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#define UDC_SR_MCH 0x0010 /* match on upper comparator byte */
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#define UDC_SR_MCL 0x0008 /* match on lower comparator byte */
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#define UDC_SR_MC 0x0004 /* match condition ended dma */
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#define UDC_SR_EOP 0x0002 /* eop condition ended dma */
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#define UDC_SR_TC 0x0001 /* termination of count ended dma */
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#endif /* !_scsi_adapters_udc_h */
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