203 lines
6.4 KiB
C
203 lines
6.4 KiB
C
/* @(#)clock.h 1.1 94/10/31 SMI */
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/*
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* Copyright (c) 1985 by Sun Microsystems, Inc.
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*/
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#ifndef _sun4_clock_h
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#define _sun4_clock_h
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/*
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* There are two types of time of day clock on Sun4 :
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* the Intersil 7170 and the Mostek 48t02.
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*/
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#define INTERSIL7170 0
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#define MOSTEK48T02 1
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/*
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* Definitions for the Intersil 7170 real-time clock. This chip
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* is used as the timer chip in addition to being the battery
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* backed up time-of-day device. This clock is run by UNIX in
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* the 100 hz periodic mode giving interrupts 100 times/second.
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*
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* Reading clk_hsec latches the the time in all the other bytes
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* so you get a consistent value. To see any byte change, you
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* have to read clk_hsec in between (e.g. you can't loop waiting
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* for clk_sec to reach a certain value without reading clk_hsec
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* each time).
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*/
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#define SECDAY ((unsigned)(24*60*60)) /* seconds per day */
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#define SECYR ((unsigned)(365*SECDAY)) /* seconds per common year */
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/*
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* The 7170 uses year % 4 to figure out if
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* we have a leap year, we do the same here.
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*/
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#define SECYEAR(yr) ((((unsigned)(yr) % 4) == 0)? SECYR + SECDAY : SECYR)
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/*
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* The year register counts from 0 to 99.
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* Unix time is the number of seconds
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* since the year YRREF. The 2 digit year
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* value stored in the chip represents the
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* the number of years beyond YRBASE.
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* Note that YRBASE must be < YRREF and
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* (YRBASE % 4) == 0 to do leap years correct.
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* Note that we can only keep time up to the year 2068.
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*/
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#define YRREF 70 /* 1970 - where UNIX time begins */
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#define YRBASE 68 /* 1968 - what year 0 in chip represents */
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#define OBIO_CLOCK_ADDR 0xF3000000 /* address of clock in obio space */
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#define CLOCK0_ADDR (MDEVBASE) /* virtual address mapped to */
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#ifndef LOCORE
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struct intersil7170 {
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u_char clk_hsec; /* counter - hundredths of seconds 0-99 */
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u_char clk_hour; /* counter - hours 0-23 (24hr) 1-12 (12hr) */
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u_char clk_min; /* counter - minutes 0-59 */
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u_char clk_sec; /* counter - seconds 0-59 */
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u_char clk_mon; /* counter - month 1-12 */
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u_char clk_day; /* counter - day 1-31 */
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u_char clk_year; /* counter - year 0-99 */
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u_char clk_weekday; /* counter - week day 0-6 */
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u_char clk_rhsec; /* RAM - hundredths of seconds 0-99 */
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u_char clk_rhour; /* RAM - hours 0-23 (24hr) 1-12 (12hr) */
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u_char clk_rmin; /* RAM - minutes 0-59 */
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u_char clk_rsec; /* RAM - seconds 0-59 */
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u_char clk_rmon; /* RAM - month 1-12 */
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u_char clk_rday; /* RAM - day 1-31 */
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u_char clk_ryear; /* RAM - year 0-99 */
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u_char clk_rweekday; /* RAM - week day 0-6 */
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u_char clk_intrreg; /* interrupt status and mask register */
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u_char clk_cmd; /* command register */
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u_char clk_unused[14];
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};
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#define CLOCK0 ((struct intersil7170 *)(CLOCK0_ADDR))
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#endif !LOCORE
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/* offsets into structure */
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#define CLK_HSEC 0
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#define CLK_HOUR 1
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#define CLK_MIN 2
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#define CLK_SEC 3
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#define CLK_MON 4
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#define CLK_DAY 5
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#define CLK_YEAR 6
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#define CLK_WEEKDAY 7
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#define CLK_RHSEC 8
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#define CLK_RHOUR 9
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#define CLK_RMIN 10
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#define CLK_RSEC 11
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#define CLK_RMON 12
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#define CLK_RDAY 13
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#define CLK_RYEAR 14
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#define CLK_RWEEKDAY 15
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#define CLK_INTRREG 16
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#define CLK_CMD 17
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/*
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* In `alarm' mode the 7170 interrupts when the current
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* counter matches the RAM values. However, if the ignore
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* bit is on in the RAM counter, that register is not
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* used in the comparision. Unfortunately, the clk_rhour
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* register uses a different mask bit (because of 12 hour
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* mode) and thus the 2 different defines.
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*/
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#define CLK_IGNORE 0x80 /* rmsec, rmin, rsec, rmon, rday, ryear, rdow */
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#define CLK_HOUR_IGNORE 0x40 /* ignore bit for clk_rhour only */
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/*
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* Interrupt status and mask register defines,
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* reading this register tells what caused an interrupt
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* and then clears the state. These can occur
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* concurrently including te RAM compare interrupts.
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*/
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#define CLK_INT_INTR 0x80 /* r/o pending interrrupt */
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#define CLK_INT_DAY 0x40 /* r/w periodic day interrupt */
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#define CLK_INT_HOUR 0x20 /* r/w periodic hour interrupt */
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#define CLK_INT_MIN 0x10 /* r/w periodic minute interrupt */
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#define CLK_INT_SEC 0x08 /* r/w periodic second interrupt */
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#define CLK_INT_TSEC 0x04 /* r/w periodic 1/10 second interrupt */
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#define CLK_INT_HSEC 0x02 /* r/w periodic 1/100 second interrupt */
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#define CLK_INT_ALARM 0x01 /* r/w alarm mode - interrupt on time match */
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/* Command register defines */
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#define CLK_CMD_TEST 0x20 /* w/o test mode (vs. normal mode) */
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#define CLK_CMD_INTRENA 0x10 /* w/o interrupt enable (vs. disabled) */
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#define CLK_CMD_RUN 0x08 /* w/o run bit (vs. stop) */
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#define CLK_CMD_24FMT 0x04 /* w/o 24 hour format (vs. 12 hour format) */
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#define CLK_CMD_F4M 0x03 /* w/o using 4.194304MHz crystal frequency */
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#define CLK_CMD_F2M 0x02 /* w/o using 2.097152MHz crystal frequency */
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#define CLK_CMD_F1M 0x01 /* w/o using 1.048576MHz crystal frequency */
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#define CLK_CMD_F32K 0x00 /* w/o using 32.768KHz crystal frequency */
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#define CLK_CMD_NORMAL (CLK_CMD_INTRENA|CLK_CMD_RUN|CLK_CMD_24FMT|CLK_CMD_F32K)
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/*
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* Definitions for the Mostek 48T02. This chip is used for the time of
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* day service (battery backed up) and combines the eeprom and TOD.
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* Machines that use this chip also include hi resolution counters which
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* provide the real-time clock. These counters are normally used to
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* generate 100hz clock interrupts, but are fully programmable for
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* whatever purpose desired.
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*/
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#define CLOCK1_ADDR (MDEVBASE + 0x27F8)
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#ifndef LOCORE
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struct mostek48T02 {
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u_char clk_ctrl;
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u_char clk_sec;
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u_char clk_min;
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u_char clk_hour;
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u_char clk_weekday;
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u_char clk_day;
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u_char clk_month;
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u_char clk_year;
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};
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#define CLOCK1 ((struct mostek48T02 *)(CLOCK1_ADDR))
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#endif !LOCORE
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#define CLK_CTRL_WRITE 0x80
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#define CLK_CTRL_READ 0x40
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#define CLK_CTRL_SIGN 0x20
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#define CLK_STOP 0x80
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#define CLK_KICK 0x80
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#define CLK_FREQT 0x40
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#define CLK_MONTH_MASK 0x1f
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#define CLK_DAY_MASK 0x3f
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#define CLK_WEEKDAY_MASK 0x07
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#define CLK_HOUR_MASK 0x3f
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#define CLK_MIN_MASK 0x7f
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#define CLK_SEC_MASK 0x7f
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#define OBIO_COUNTER_ADDR 0xEF000000
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#define COUNTER_ADDR (MDEVBASE + 0xA000)
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#ifndef LOCORE
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struct counterregs {
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u_int counter10;
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u_int limit10;
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u_int counter14;
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u_int limit14;
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};
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#define COUNTER ((struct counterregs *)(COUNTER_ADDR))
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#endif !LOCORE
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#define CTR_LIMIT_BIT 0x80000000 /* limit bit mask */
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#define CTR_USEC_MASK 0x7FFFFC00 /* counter/limit mask */
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#define CTR_USEC_SHIFT 10 /* counter/limit shift */
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/*
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* Offsets into counter register structure.
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*/
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#define COUNT10 0
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#define LIM10 4
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#define COUNT14 8
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#define LIM14 12
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#endif /*!_sun4_clock_h*/
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