155 lines
3.2 KiB
ArmAsm
155 lines
3.2 KiB
ArmAsm
/* @(#)map.s 1.1 94/10/31 */
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!
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! Copyright (c) 1986 by Sun Microsystems, Inc.
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!
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/*
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* Additional memory mapping routines for use by standalone debugger,
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* setpgmap(), getpgmap() are taken from the boot code.
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*/
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#include "asm_linkage.h"
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#include "assym.s"
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#include <sys/param.h>
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#include <sun4/mmu.h>
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#include <sun4/pte.h>
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#include <sun4/enable.h>
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#include <sun4/cpu.h>
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#include "../../debug/debug.h"
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.seg "text"
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.align 4
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/*
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* Read the page map entry for the given address v
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* and return it in a form suitable for software use.
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*
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* long
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* Getpgmap(v)
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* caddr_t v;
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*/
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ENTRY(Getpgmap)
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andn %o0, 0x3, %o1 ! align to word boundary
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lda [%o1]ASI_PM, %o0 ! read page map entry
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retl
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nop
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/*
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* Set the pme for address v using the software pte given.
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* Setpgmap() automatically turns on the ``no cache'' bit
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* for all mappings between DEBUGSTART and DEBUGEND.
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*
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* Setpgmap(v, pte)
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* caddr_t v;
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* long pte;
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*/
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ENTRY(Setpgmap)
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set DEBUGSTART, %o2 ! skip ahead if before debugger
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cmp %o0, %o2
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blu 1f
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.empty ! delay slot ok
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set DEBUGEND, %o2 ! skip ahead if after debugger
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cmp %o0, %o2
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bgeu 1f
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.empty ! delay slot ok
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set PG_NC, %o2 ! set don't cache bit
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or %o1, %o2, %o1
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1:
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andn %o0, 0x3, %o2 ! align to word boundary
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retl
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sta %o1, [%o2]ASI_PM ! write page map entry
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/*
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* Get the segment map entry for ther given virtual address
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*
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* Getsegmap(v)
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* caddr_t vaddr;
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*/
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.global _Getsegmap
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_Getsegmap:
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andn %o0, 0x1, %o0 ! get relevant segment address bits
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lduha [%o0]ASI_SM,%o0 ! read segment entry
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set _segmask, %o2 ! need to mask bits due to bug in cobra
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ld [%o2], %o2
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retl
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and %o0, %o2, %o0
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/*
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* Set the segment map entry for ther given virtual address
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*
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* Setsegmap(v, segm)
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* caddr_t vaddr;
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*/
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.global _Setsegmap
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_Setsegmap:
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andn %o0, 0x1, %o0 ! get relevant segment address bits
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set _segmask, %o2 ! need to mask bits due to bug in cobra
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ld [%o2], %o2
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and %o1, %o2, %o1
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retl
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stha %o1, [%o0]ASI_SM
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/*
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* Set the current context number to 0.
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*
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* setcontext()
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*/
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ENTRY(setkcontext)
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set CONTEXT_REG, %o0
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retl
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stba %g0, [%o0]ASI_CTL ! write the context register
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/*
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* get the machine type in the ID prom.
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*
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* u_char
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* getmachinetype()
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*/
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ENTRY(getmachinetype)
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set ID_PROM+1, %o0
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retl
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lduba [%o0]ASI_CTL, %o0
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/*
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* Flush a page from the cache.
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*
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* vac_pageflush(vaddr)
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* caddr_t vaddr;
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*/
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ENTRY(vac_pageflush)
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srl %o0, PGSHIFT, %o0 ! mask off low bits
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sll %o0, PGSHIFT, %o0
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set _vac_linesize, %o1 ! linesize
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ld [%o1], %o1
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set _vac_pglines, %o2 ! number of lines in a page
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ld [%o2], %o2
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1:
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sta %g0, [%o0]ASI_FCP ! flush a line, page match
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deccc %o2 ! decrement count
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bg 1b ! done yet?
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add %o0, %o1, %o0 ! generate next match address
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2:
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retl
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nop
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!
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! Initialize the cache by invalidating all the cache tags.
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! It DOESN'T turn on cache enable bit in the enable register.
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!
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! void
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! vac_tagsinit()
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!
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ENTRY(vac_tagsinit)
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set _vac_linesize, %o0 ! linesize
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ld [%o0], %o2
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set VAC_SIZE, %o1 ! size of cache
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set CACHE_TAGS, %o0 ! address of cache tags in CTL space
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1:
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subcc %o1, %o2, %o1 ! done yet?
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bgu 1b
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sta %g0, [%o0 + %o1]ASI_CTL ! write tags to zero
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retl
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nop
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