35 lines
992 B
C
35 lines
992 B
C
/* @(#)enable.h 1.1 94/10/31 SMI */
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/*
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* Copyright (c) 1987 by Sun Microsystems, Inc.
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*/
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/*
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* The System Enable register controls overall
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* operation of the system. When the system is
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* reset, the Enable register is cleared. The
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* enable register is addressed as a byte in
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* ASI_CTL space.
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*/
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#ifndef _sun4_enable_h
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#define _sun4_enable_h
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/*
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* Bits of the Enable Register
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*/
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#define ENA_DIAG 0x01 /* r/o - diag switch, 1 = on */
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#define ENA_MONITOR 0x01 /* w/o - monitor bit */
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#define ENA_VMERESET 0x02 /* r/w - reset the vme */
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#define ENA_CACHERESET 0x04 /* r/w - reset the cache */
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#define ENA_VIDEO 0x08 /* r/w - enable video memory */
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#define ENA_CACHE 0x10 /* r/w - enable external cache */
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#define ENA_SDVMA 0x20 /* r/w - enable system DVMA */
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#define ENA_IOCACHE 0x40 /* r/w - enable i/o cache */
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#define ENA_NOTBOOT 0x80 /* r/w - non-boot state, 1 = normal */
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#define ENABLEREG 0x40000000 /* addr in ASI_CTL space */
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#endif /*!_sun4_enable_h*/
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