528 lines
12 KiB
ArmAsm
528 lines
12 KiB
ArmAsm
.ident "@(#)map.s 1.1 94/10/31 SMI"
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/*
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* Copyright 1988-1989 Sun Microsystems, Inc.
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*/
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/*
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* Sun-4c MMU and Virtual Address Cache routines.
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*
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* Notes:
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*
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* - Supports write-through caches only.
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* - Hardware cache flush must work in page size chunks.
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* - Cache size <= 1 MB, line size <= 256 bytes.
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* - Assumes vac_flush() performance is not critical.
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*/
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#include <sys/param.h>
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#include <machine/asm_linkage.h>
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#include <machine/mmu.h>
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#include <machine/pte.h>
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#include <machine/enable.h>
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#include "assym.s"
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.seg "text"
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.align 4
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!
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! Read the page map entry for the given address v
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! and return it in a form suitable for software use.
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!
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! u_int
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! map_getpgmap(v)
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! addr_t v;
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!
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ENTRY(map_getpgmap)
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andn %o0, 0x3, %o1 ! align to word boundary
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retl
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lda [%o1]ASI_PM, %o0 ! read page map entry
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!
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! Set the pme for address v using the software pte given.
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!
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! map_setpgmap(v, pte)
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! addr_t v;
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! u_int pte;
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!
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ENTRY(map_setpgmap)
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andn %o0, 0x3, %o2 ! align to word boundary
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retl
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sta %o1, [%o2]ASI_PM ! write page map entry
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!
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! Return the 16 bit segment map entry for the given segment number.
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!
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! u_int
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! map_getsgmap(v)
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! addr_t v;
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!
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ENTRY(map_getsgmap)
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lduba [%o0]ASI_SM, %o0 ! read segment number
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retl
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and %o0, 0xff, %o0 ! mask off top bit
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!
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! Set the segment map entry for segno to pm.
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!
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! map_setsgmap(v, pm)
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! addr_t v;
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! u_int pm;
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!
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ENTRY(map_setsgmap)
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retl
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stba %o1, [%o0]ASI_SM ! write segment entry
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!
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! Return the current context number.
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!
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! u_int
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! map_getctx()
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!
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ENTRY(map_getctx)
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set CONTEXT_REG, %o1
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retl
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lduba [%o1]ASI_CTL, %o0 ! read the context register
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!
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! Set the current context number.
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!
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! map_setctx(c)
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! u_int c;
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!
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ENTRY(map_setctx)
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set CONTEXT_REG, %o1
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retl
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stba %o0, [%o1]ASI_CTL ! write the context register
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/*
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* cache config word: _vac_info
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*/
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#if 0
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struct {
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vi_size : 21; /* cache size, bytes */
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vi_vac : 1; /* vac enabled */
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vi_hw : 1; /* HW flush */
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vi_linesize : 9; /* line size, bytes */
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} vac_info;
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#endif 0
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.reserve vac_info, 4, "bss", 4
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#define VAC_INFO_VSS 11 /* VAC size shift (32 - 21) */
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#define VAC_INFO_VAC (0x400) /* VAC bit */
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#define VAC_INFO_HW (0x200) /* HW flush bit */
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#define VAC_INFO_LSM (0x1ff) /* line size mask */
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/* note: safe in .empty slot */
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#define GET(val,p,d) \
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sethi %hi(val), p; \
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ld [p + %lo(val)], d ;
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#define GET_INFO(p,d) GET(vac_info,p,d)
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!
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! Set up VAC config word from imported variables, set vac, clear tags,
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! enable/disable cache.
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!
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! void
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! vac_control(on)
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!
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ENTRY(vac_control)
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! encode VAC params
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GET(_vac_size, %g1, %o1) ! get VAC size
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GET(_vac_hwflush, %g2, %o2) ! get HW flush flag
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GET(_vac_linesize, %g1, %o3) ! get line size
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sll %o1, VAC_INFO_VSS, %o1 ! encode VAC size
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sethi %hi(_vac), %g2 ! prepare to write "vac"
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tst %o2 ! HW flush?
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bz 1f
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st %o0, [%g2 + %lo(_vac)] ! write "vac"
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bset VAC_INFO_HW, %o1 ! encode HW flush
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1: tst %o0 ! enabling VAC?
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bz 2f
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bset %o3, %o1 ! merge line size
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bset VAC_INFO_VAC, %o1 ! encode VAC enabled
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2: sethi %hi(vac_info), %g1 ! prepare to write vac_info
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set _off_enablereg, %g2 ! prepare to disable
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bz 3f
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st %o1, [%g1 + %lo(vac_info)] ! write vac_info
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! enabling cache
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mov %o7, %g1 ! save ret addr
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call _vac_flushall ! flush cache
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.empty
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set _on_enablereg, %g2 ! prepare to enable
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mov %g1, %o7 ! restore ret addr
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! do it
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3: jmp %g2
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mov ENA_CACHE, %o0
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!
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! Initialize the cache by invalidating all the cache tags.
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! DOES NOT turn on cache enable bit in the enable register.
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!
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! void
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! vac_flushall()
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!
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ENTRY(vac_flushall)
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GET_INFO(%o5, %o2) ! get VAC info
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set CACHE_TAGS, %o3 ! address of cache tags in CTL space
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srl %o2, VAC_INFO_VSS, %o1 ! cache size
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and %o2, VAC_INFO_LSM, %o2 ! line size
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#ifdef SIMUL
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/*
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* Don't clear entire cache in the hardware simulator,
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* it takes too long and the simulator has already cleared it
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* for us.
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*/
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set 256, %o1 ! initialize only 256 bytes worth
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#endif SIMUL
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1: subcc %o1, %o2, %o1 ! done yet?
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bg 1b
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sta %g0, [%o3+%o1]ASI_CTL ! clear tag
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retl
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.empty
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!
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! Flush a context from the cache.
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! To flush a context we must cycle through all lines of the
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! cache issuing a store into alternate space command for each
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! line whilst the context register remains constant.
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!
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! void
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! vac_ctxflush()
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!
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ENTRY(vac_ctxflush)
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GET_INFO(%o5, %o2) ! get VAC info
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sethi %hi(_flush_cnt+FM_CTX), %g1 ! get flush count
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btst VAC_INFO_VAC, %o2 ! check if cache is turned on
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bz 9f ! cache off, return
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srl %o2, VAC_INFO_VSS, %o1 ! cache size
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ld [%g1 + %lo(_flush_cnt+FM_CTX)], %g2 ! get flush count
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btst VAC_INFO_HW, %o2 ! HW flush?
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inc %g2 ! increment flush count
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bz 2f ! use SW flush
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st %g2, [%g1 + %lo(_flush_cnt+FM_CTX)] ! store flush count
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! hardware flush
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set NBPG, %o2
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1: subcc %o1, %o2, %o1
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bg 1b
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sta %g0, [%o1]ASI_FCC_HW
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retl
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.empty
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! software flush
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2: and %o2, VAC_INFO_LSM, %o2 ! line size
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add %o2, %o2, %o3 ! LS * 2
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add %o2, %o3, %o4 ! LS * 3
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add %o2, %o4, %o5 ! LS * 4
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add %o2, %o5, %g1 ! LS * 5
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add %o2, %g1, %g2 ! LS * 6
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add %o2, %g2, %g3 ! LS * 7
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add %o2, %g3, %g4 ! LS * 8
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3: subcc %o1, %g4, %o1
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sta %g0, [%o1 + %g0]ASI_FCC
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sta %g0, [%o1 + %o2]ASI_FCC
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sta %g0, [%o1 + %o3]ASI_FCC
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sta %g0, [%o1 + %o4]ASI_FCC
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sta %g0, [%o1 + %o5]ASI_FCC
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sta %g0, [%o1 + %g1]ASI_FCC
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sta %g0, [%o1 + %g2]ASI_FCC
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bg 3b
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sta %g0, [%o1 + %g3]ASI_FCC
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9: retl
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.empty
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!
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! Flush a segment from the cache.
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! To flush the argument segment from the cache we hold the bits that
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! specify the segment in the address constant and issue a store into
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! alternate space command for each line.
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!
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! vac_segflush(v)
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! addr_t v;
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!
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ENTRY(vac_segflush)
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GET_INFO(%o5, %o2) ! get VAC info
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sethi %hi(_flush_cnt+FM_SEGMENT), %g1 ! get flush count
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btst VAC_INFO_VAC, %o2 ! check if cache is turned on
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bz 9f ! cache off, return
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srl %o2, VAC_INFO_VSS, %o1 ! cache size
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ld [%g1 + %lo(_flush_cnt+FM_SEGMENT)], %g2 ! get flush count
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btst VAC_INFO_HW, %o2 ! HW flush?
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inc %g2 ! increment flush count
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srl %o0, PMGRPSHIFT, %o0 ! get segment part of address
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sll %o0, PMGRPSHIFT, %o0
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bz 2f ! use SW flush
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st %g2, [%g1 + %lo(_flush_cnt+FM_SEGMENT)] ! store flush count
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! hardware flush
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set NBPG, %o2
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1: subcc %o1, %o2, %o1
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bg 1b
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sta %g0, [%o0 + %o1]ASI_FCS_HW
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retl
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.empty
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! software flush
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2: and %o2, VAC_INFO_LSM, %o2 ! line size
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add %o2, %o2, %o3 ! LS * 2
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add %o2, %o3, %o4 ! LS * 3
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add %o2, %o4, %o5 ! LS * 4
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add %o2, %o5, %g1 ! LS * 5
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add %o2, %g1, %g2 ! LS * 6
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add %o2, %g2, %g3 ! LS * 7
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add %o2, %g3, %g4 ! LS * 8
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3: subcc %o1, %g4, %o1
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sta %g0, [%o0 + %g0]ASI_FCS
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sta %g0, [%o0 + %o2]ASI_FCS
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sta %g0, [%o0 + %o3]ASI_FCS
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sta %g0, [%o0 + %o4]ASI_FCS
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sta %g0, [%o0 + %o5]ASI_FCS
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sta %g0, [%o0 + %g1]ASI_FCS
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sta %g0, [%o0 + %g2]ASI_FCS
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sta %g0, [%o0 + %g3]ASI_FCS
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bg 3b
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add %o0, %g4, %o0
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9: retl
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.empty
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!
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! Flush a page from the cache.
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! To flush the page containing the argument virtual address from
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! the cache we hold the bits that specify the page constant and
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! issue a store into alternate space command for each line.
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!
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! vac_pageflush(v)
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! addr_t v;
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!
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ENTRY(vac_pageflush)
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GET_INFO(%o5, %o2) ! get VAC info
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sethi %hi(_flush_cnt+FM_PAGE), %g1 ! get flush count
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btst VAC_INFO_VAC, %o2 ! check if cache is turned on
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bz 9f ! cache off, return
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set NBPG, %o1 ! page size
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ld [%g1 + %lo(_flush_cnt+FM_PAGE)], %g2 ! get flush count
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btst VAC_INFO_HW, %o2 ! HW flush?
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inc %g2 ! increment flush count
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bz 2f ! use SW flush
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st %g2, [%g1 + %lo(_flush_cnt+FM_PAGE)] ! store flush count
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! hardware flush
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bclr 3,%o0 ! force word alignment
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retl
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sta %g0, [%o0]ASI_FCP_HW
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! software flush
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2:
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#if PGSHIFT <= 13
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bclr (NBPG - 1), %o0 ! get page part of address
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#else
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srl %o0, PGSHIFT, %o0 ! get page part of address
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sll %o0, PGSHIFT, %o0
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#endif
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and %o2, VAC_INFO_LSM, %o2 ! line size
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add %o2, %o2, %o3 ! LS * 2
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add %o2, %o3, %o4 ! LS * 3
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add %o2, %o4, %o5 ! LS * 4
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add %o2, %o5, %g1 ! LS * 5
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add %o2, %g1, %g2 ! LS * 6
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add %o2, %g2, %g3 ! LS * 7
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add %o2, %g3, %g4 ! LS * 8
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3: subcc %o1, %g4, %o1
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sta %g0, [%o0 + %g0]ASI_FCP
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sta %g0, [%o0 + %o2]ASI_FCP
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sta %g0, [%o0 + %o3]ASI_FCP
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sta %g0, [%o0 + %o4]ASI_FCP
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sta %g0, [%o0 + %o5]ASI_FCP
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sta %g0, [%o0 + %g1]ASI_FCP
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sta %g0, [%o0 + %g2]ASI_FCP
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sta %g0, [%o0 + %g3]ASI_FCP
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bg 3b
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add %o0, %g4, %o0
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9: retl
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.empty
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!
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! Flush a range of addresses.
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!
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! vac_flush(v, nbytes)
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! addr_t v;
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! u_int nbytes;
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!
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ENTRY(vac_flush)
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GET_INFO(%o5, %o2) ! get VAC info
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sethi %hi(_flush_cnt+FM_PARTIAL), %g1 ! get flush count
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btst VAC_INFO_VAC, %o2 ! check if cache is turned on
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bz 9f ! cache off, return
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srl %o2, VAC_INFO_VSS, %o3 ! cache size
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ld [%g1 + %lo(_flush_cnt+FM_PARTIAL)], %g2 ! get flush count
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and %o2, VAC_INFO_LSM, %o2 ! line size
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sub %o2, 1, %o4 ! convert to mask (assumes power of 2 )
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inc %g2 ! increment flush count
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st %g2, [%g1 + %lo(_flush_cnt+FM_PARTIAL)] ! store flush count
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add %o0, %o1, %o1 ! add start to length
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andn %o0, %o4, %o0 ! round down start
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add %o4, %o1, %o1 ! round up end
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andn %o1, %o4, %o1 ! and mask off
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sub %o1, %o0, %o1 ! and subtract start
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cmp %o1, %o3 ! if (nbytes > vac_size)
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bgu,a 1f ! ...
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mov %o3, %o1 ! nbytes = vac_size
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1: ! nop
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2: subcc %o1, %o2, %o1
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bg 2b
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sta %g0, [%o0 + %o1]ASI_FCP
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9: retl
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nop
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!
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! Mark a page as noncachable.
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!
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! void
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! vac_dontcache(p)
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! addr_t p;
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!
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ENTRY(vac_dontcache)
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andn %o0, 0x3, %o1 ! align to word boundary
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lda [%o1]ASI_PM, %o0 ! read old page map entry
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set PG_NC, %o2
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or %o0, %o2, %o0 ! turn on NOCACHE bit
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retl
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sta %o0, [%o1]ASI_PM ! and write it back out
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!
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! Flush all user lines from the cache. We accomplish it by reading a portion
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! of the kernel text starting at sys_trap. The size of the portion is
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! equal to the VAC size. We read a word from each line. sys_trap was chosen
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! as the start address because it is the start of the locore code
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! that we assume will be very likely executed in near future.
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!
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! XXX - use a HW feature if the cache supports it (e.g. SunRay).
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!
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ENTRY(vac_usrflush)
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GET_INFO(%o5, %o2) ! get VAC info
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btst VAC_INFO_VAC, %o2 ! check if cache is turned on
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bnz,a 1f ! cache on
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save %sp, -SA(MINFRAME), %sp
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retl
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nop
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1:
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call _flush_user_windows ! make sure no windows are hanging out
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nop
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sethi %hi(_flush_cnt+FM_USR), %g1 ! get flush count
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ld [%g1 + %lo(_flush_cnt+FM_USR)], %g2 ! get flush count
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!
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! Due to a bug in HW, some processor must map the trap vectors
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! non cacheable. Software (locore.s) must guarantee that the
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! code that follows the trap vectors starts in next page.
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! We are paranoid about it and check that sys_trap is actually
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! in a cacheable page. We panic otherwise.
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!
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tst %g2
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set sys_trap, %i0 ! start reading text seg. from sys_trap
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bnz 2f
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inc %g2 ! increment flush count
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! check pte only the first time we vac_usrflush is called
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lda [%i0]ASI_PM, %l0 ! read page map entry
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set PG_NC, %l1
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btst %l1, %l0
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bz 2f
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nop
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sethi %hi(6f), %o0
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call _panic
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or %o0, %lo(6f), %o0
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.seg "data"
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6: .asciz "vac_usrflush: sys_trap is not in cacheable page"
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.seg "text"
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2:
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st %g2, [%g1 + %lo(_flush_cnt+FM_USR)] ! store flush count
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GET(_vac_size, %l1, %i1) ! cache size
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and %i2, VAC_INFO_LSM, %i2 ! line size
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!
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! A flush that causes a writeback will happen in parallel
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! with other instructions. Back to back flushes which cause
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! writebacks cause the processor to wait until the first writeback
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! is finished and the second is initiated before proceeding.
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! Avoid going through the cache sequentially by flushing
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! 16 lines spread evenly through the cache.
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!
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! i0 start address
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! i1 vac_size
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! i2 linesize
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srl %i1, 4, %l0 ! vac_size / 16
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add %l0, %l0, %l1 ! 2 * (vac_size / 16)
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add %l1, %l0, %l2 ! ...
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add %l2, %l0, %l3
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add %l3, %l0, %l4
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add %l4, %l0, %l5
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add %l5, %l0, %l6
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add %l6, %l0, %l7
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add %l7, %l0, %o0
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add %o0, %l0, %o1
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add %o1, %l0, %o2
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add %o2, %l0, %o3
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add %o3, %l0, %o4
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add %o4, %l0, %o5
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add %o5, %l0, %i4 ! 15 * (vac_size / 16)
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mov %l0, %i3 ! loop counter: vac_size / 16
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3:
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ld [%i0 ], %i1
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ld [%i0 + %l0], %i1
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ld [%i0 + %l1], %i1
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ld [%i0 + %l2], %i1
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ld [%i0 + %l3], %i1
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ld [%i0 + %l4], %i1
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ld [%i0 + %l5], %i1
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ld [%i0 + %l6], %i1
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ld [%i0 + %l7], %i1
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ld [%i0 + %o0], %i1
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ld [%i0 + %o1], %i1
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ld [%i0 + %o2], %i1
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ld [%i0 + %o3], %i1
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ld [%i0 + %o4], %i1
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ld [%i0 + %o5], %i1
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ld [%i0 + %i4], %i1
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subcc %i3, %i2, %i3 ! decrement loop count
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bg 3b ! are we done yet?
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|
add %i0, %i2, %i0 ! generate next addr
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ret
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restore
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