303 lines
7.1 KiB
ArmAsm
303 lines
7.1 KiB
ArmAsm
.ident "@(#)map.s 1.1 94/10/31 SMI"
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!
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! Copyright (c) 1986 by Sun Microsystems, Inc.
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!
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/*
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* Additional memory mapping routines for use by standalone debugger,
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* setpgmap(), getpgmap() are taken from the boot code.
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*/
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#include "assym.s"
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#include <sys/param.h>
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#include <machine/mmu.h>
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#include <machine/pte.h>
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#include <machine/enable.h>
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#include <machine/cpu.h>
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#include <machine/psl.h>
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#include <machine/eeprom.h>
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#include <machine/asm_linkage.h>
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#include <machine/reg.h>
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#include <debug/debug.h>
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.seg "data"
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ross625_line_size:
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.word 64
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.seg "text"
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.align 4
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#define CACHE_LINESHFT 5
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#define CACHE_LINESZ (1<<CACHE_LINESHFT)
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/*
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* Flush a page from the cache.
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*
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* vac_pageflush(vaddr)
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* caddr_t vaddr;
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*/
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ENTRY(vac_pageflush)
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sethi %hi(_v_vac_pageflush), %g1
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ld [%g1+%lo(_v_vac_pageflush)], %g1
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jmp %g1
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nop
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ENTRY(ross_vac_pageflush)
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set PAGESIZE/8, %g1
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add %o0, %g1, %o1
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add %o1, %g1, %o2
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add %o2, %g1, %o3
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add %o3, %g1, %o4
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add %o4, %g1, %o5
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add %o5, %g1, %g2
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add %g2, %g1, %g3
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1: deccc CACHE_LINESZ, %g1
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sta %g0, [%o0 + %g1]ASI_FCP
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sta %g0, [%o1 + %g1]ASI_FCP
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sta %g0, [%o2 + %g1]ASI_FCP
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sta %g0, [%o3 + %g1]ASI_FCP
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sta %g0, [%o4 + %g1]ASI_FCP
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sta %g0, [%o5 + %g1]ASI_FCP
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sta %g0, [%g2 + %g1]ASI_FCP
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bne 1b
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sta %g0, [%g3 + %g1]ASI_FCP
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retl
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nop
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/* ************** start ROSS 620/625 support ************** */
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#define RT625_CACHE_LINES 4096
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#define RT625_SMALL_LINESIZE 32
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#define RT625_BIG_LINESIZE 64
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#define RT625_CTL_CE 0x00000100 /* cache enable */
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#define RT625_CTL_CS 0x00001000 /* cache size */
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#define RT625_ASI_CTAGS 0x0e /* cache tags */
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#define RT620_ASI_IC 0x31 /* icache control */
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#define GET(val, r) \
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sethi %hi(val), r; \
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ld [r+%lo(val)], r
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#define PUT(val, r, t) \
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sethi %hi(val), t; \
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st r, [t+%lo(val)]
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/*
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* ross625_cache_init - initialize ross 625 cache
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* 1) figure out the line size from the MMU ctl reg
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* 2) clear the cache
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* 3) turn off the cache
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* 4) clear the cache tags
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* 5) clear the icache
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*/
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ENTRY(ross625_cache_init)
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set RMMU_CTL_REG, %o0
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lda [%o0]ASI_MOD, %o1 ! get the MMU ctl reg
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set RT625_CTL_CS, %o2
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andcc %o2, %o1, %o2
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bz 1f
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nop
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mov RT625_BIG_LINESIZE,%o3 ! CS on = 64 byte line size
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b 2f
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nop
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1: mov RT625_SMALL_LINESIZE,%o3 ! CS off = 32 byte line size
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2: PUT(ross625_line_size, %o3, %o2)
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set RT625_CACHE_LINES,%o2 ! clear cache
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GET(ross625_line_size,%o3)
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mov 0, %o4
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1: sta %g0, [%o4]ASI_FCC
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subcc %o2, 1, %o2
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bnz 1b
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add %o4, %o3, %o4
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set RMMU_CTL_REG, %o0 ! turn cache off
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lda [%o0]ASI_MOD, %o1
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andn %o1, RT625_CTL_CE, %o1
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sta %o1, [%o0]ASI_MOD
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set RT625_CACHE_LINES, %o2 ! clear cache tags
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GET(ross625_line_size,%o3)
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mov 0, %o4
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1: sta %g0, [%o4]RT625_ASI_CTAGS
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subcc %o2, 1, %o2
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bnz 1b
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add %o4, %o3, %o4
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retl
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sta %g0, [%g0]RT620_ASI_IC ! clear the icache
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/*
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* ross625_cache_on - turn the cache on
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*/
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ENTRY(ross625_cache_on)
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set RT625_CTL_CE, %o2 ! cache enable
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set RMMU_CTL_REG, %o0 ! mmu control reg
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lda [%o0]ASI_MOD, %o1
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or %o1, %o2, %o1
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retl
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sta %o1, [%o0]ASI_MOD
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/*
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* ross625_vac_pageflush - flush the cache for the page in %o0
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*/
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ENTRY(ross625_vac_pageflush)
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set PAGESIZE, %o1 ! the page size
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GET(ross625_line_size,%o2) ! the line size
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1: subcc %o1, %o2, %o1 ! for all the lines in a page
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sta %g0, [%o0]ASI_FCP ! flush cache line (PAGE)
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bne 1b
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add %o0, %o2, %o0 ! on to the next line
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retl
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sta %g0, [%g0]RT620_ASI_IC ! clear the icache
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/*
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* ross625_vac_flushall - flush the entire cache and TLB
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*/
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ENTRY(ross625_vac_flushall)
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set RT625_CACHE_LINES, %o0 ! for all the lines
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GET(ross625_line_size, %o1) ! a line at a time
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mov 0, %o2
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1: sta %g0, [%o2]ASI_FCC ! clear the cache line
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subcc %o0, 1, %o0 ! for all the lines
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bnz 1b
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add %o2, %o1, %o2 ! on to next line
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mov FT_ALL<<8, %g1
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retl
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sta %g0, [%g1]ASI_FLPR ! flush the tags
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/* ************** end ROSS 620/625 support ************** */
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#define SWIFT_CACHE_LINESHIFT 4
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#define SWIFT_CACHE_LINESZ (1<<SWIFT_CACHE_LINESHIFT)
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#define Faddr %o0
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#define Addr %o1
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#define Tmp1 %o2
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#define Tmp2 %o3
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#define Tmp3 %o4
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#define Tmp4 %o5
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#define Tmp5 %g3
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#define Tmp6 %g4
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#define Tmp7 %g5
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ENTRY(swift_vac_pageflush)
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set PAGESIZE/8, Addr
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mov Addr, Tmp1
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add Tmp1, Addr, Tmp2
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add Tmp2, Addr, Tmp3
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add Tmp3, Addr, Tmp4
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add Tmp4, Addr, Tmp5
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add Tmp5, Addr, Tmp6
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add Tmp6, Addr, Tmp7
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1: deccc SWIFT_CACHE_LINESZ, Addr
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sta %g0, [Faddr ]ASI_FCP
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sta %g0, [Faddr + Tmp1]ASI_FCP
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sta %g0, [Faddr + Tmp2]ASI_FCP
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sta %g0, [Faddr + Tmp3]ASI_FCP
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sta %g0, [Faddr + Tmp4]ASI_FCP
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sta %g0, [Faddr + Tmp5]ASI_FCP
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sta %g0, [Faddr + Tmp6]ASI_FCP
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sta %g0, [Faddr + Tmp7]ASI_FCP
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bne 1b
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inc SWIFT_CACHE_LINESZ, Faddr
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retl
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nop
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/*
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* int ldphys(int paddr)
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* read word of memory at physical address
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* also called "ldphys" by some codes
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*/
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ENTRY(ldphys)
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sethi %hi(_cache), %o1
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ld [%o1 + %lo(_cache)], %o1
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cmp %o1, CACHE_PAC_E ! Viking/E$
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bnz,a 0f ! No,
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lda [%o0]ASI_MEM, %o0 ! dont need AC bit set
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mov %psr, %o1 ! Save %psr in %o1
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andn %o1, PSR_ET, %g1 ! disable traps
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mov %g1, %psr
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nop; nop; nop ! PSR delay
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lda [%g0]ASI_MOD, %o2 ! get MMU CSR, %o2 keeps the saved CSR
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set CPU_VIK_AC, %o3 ! AC bit
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or %o2, %o3, %o3 ! or in AC bit
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sta %o3, [%g0]ASI_MOD ! store new CSR
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lda [%o0]ASI_MEM, %o0
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sta %o2, [%g0]ASI_MOD ! restore CSR;
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mov %o1, %psr ! restore psr; enable traps again
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nop ! PSR delay
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0:
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retl
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nop
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/*
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* void stphys(int paddr, int data)
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* write word of memory at physical address
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*/
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ENTRY(stphys)
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sethi %hi(_cache), %o4
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ld [%o4 + %lo(_cache)], %o4
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cmp %o4, CACHE_PAC_E ! Viking/E$?
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bnz,a 0f ! No, dont need AC bit set
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sta %o1, [%o0]ASI_MEM
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mov %psr, %o4 ! Save %psr in %o4
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andn %o4, PSR_ET, %g1 ! disable traps
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mov %g1, %psr
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nop; nop; nop ! PSR delay
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lda [%g0]ASI_MOD, %o2 ! get MMU CSR, %o2 keeps the saved CSR
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set CPU_VIK_AC, %o3 ! AC bit
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or %o2, %o3, %o3 ! or in AC bit
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sta %o3, [%g0]ASI_MOD ! store new CSR
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sta %o1, [%o0]ASI_MEM
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sta %o2, [%g0]ASI_MOD ! restore CSR;
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mov %o4, %psr ! restore psr; enable traps again
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nop ! PSR delay
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0:
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retl
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nop
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/*
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* void mmu_flushall()
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* flush all entries from TLB
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* XXX - for the moment this will only work with GENERIC SRMMU
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* modules, also MP is not supported.
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*/
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ENTRY(mmu_flushall)
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sethi %hi(_v_mmu_flushall), %g1
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ld [%g1+%lo(_v_mmu_flushall)], %g1
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jmp %g1
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nop
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ENTRY(srmmu_flushall)
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or %g0, FT_ALL << 8, %o0
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sta %g0, [%o0]ASI_FLPR
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retl
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nop ! let mmu settle ??
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/*
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* int mmu_getctp(void)
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* return current context table pointer
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*/
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ENTRY(mmu_getctp) ! int mmu_getctp(void);
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set RMMU_CTP_REG, %o1 ! get srmmu context table ptr
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retl
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lda [%o1]ASI_MOD, %o0
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